AD7298-1 Analog Devices, AD7298-1 Datasheet - Page 16

• Manufacturer Part Number: AD7298-1
• Description: 8-Channel, 1 MSPS, 10-Bit SAR ADC
• Manufacturer: Analog Devices

Specifications of AD7298-1

• Resolution (bits): 10bit
• # Chan: 8
• Sample Rate: 1MSPS
• Interface: SPI
• Analog Input Type: SE-Uni
• Ain Range: Uni (Vref),Uni 1.0V,Uni 1.25,Uni 2.0V,Uni 2.5V
• Adc Architecture: SAR
• Pkg Type: CSP

AD7298-1
MODES OF OPERATION
The AD7298-1 offers different modes of operation that are
designed to provide additional flexibility for the user. These
options can be chosen by programming the content of the
control register to select the desired mode.
TRADITIONAL MULTICHANNEL MODE OF
OPERATION
The AD7298-1 can operate as a traditional multichannel ADC,
where each serial transfer selects the next channel for conversion.
One must write to the control register to configure and select
the desired input channel prior to initiating any conversions. In
the traditional mode of operation, the CS signal is used to frame
the first write to the converter on the DIN pin. In this mode of
operation, the REPEAT bit in the control register is set to a low
logic level (0), therefore the REPEAT function is not in use. The
data, which appears on the DOUT pin during the initial write to
the control register, is invalid. The first CS falling edge initiates a
write to the control register to configure the device; a conversion is
then initiated for the selected analog input channel (V
DOUT
SCLK
DIN
CS
1
REGISTER CHANNEL 1 SELECTED
DATA WRITTEN TO CONTROL
DOUT
DOUT
SCLK
SCLK
DIN
DIN
CS
CS
INVALID DATA
10
Figure 24. Configuring a Conversion and Read with the AD7298-1, Numerous Channels Selected for Conversion
1
1
REGISTER CH 1 AND 2 SELECTED
DATA WRITTEN TO CONTROL
Figure 23. Configuring a Conversion and Read with the AD7298-1, One Channel Selected for Conversion
CONVERSION RESULT
CONTROL REGISTER
NO WRITE TO THE
FOR CHANNEL 2
INVALID DATA
16
10
1
REGISTER CHANNEL 4 SELECTED
DATA WRITTEN TO CONTROL
16
16
INVALID DATA
IN0
1
1
) on the
CONVERSION RESULT
CONTROL REGISTER
CONTROL REGISTER
Rev. A | Page 16 of 24
NO WRITE TO THE
NO WRITE TO THE
FOR CHANNEL 5
INVALID DATA
16
subsequent (second) CS falling edge; and the third CS falling edge
will have the result (V
operates with one cycle latency, therefore the conversion result
corresponding to each conversion is available one serial read
cycle after the cycle in which the conversion was initiated.
As the device operates with one cycle latency, the control
register configuration sets up the configuration for the next
conversion, which is initiated on the next CS falling edge, but
the first bit of the corresponding result is not clocked out until
the subsequent falling CS edge, as shown in Figure 23.
If more than one channel is selected in the control register, the
AD7298-1 converts all selected channels sequentially in ascending
order on successive CS falling edges. Once all the selected channels
in the control register are converted, the AD7298-1 ceases converting
until the user rewrites to the control register to select the next
channel for conversion. This operation is shown in Figure 24.
DOUT returns all 1s if the sequence of conversions is completed or
if no channel is selected.
1
16
16
CONVERSION RESULT
CONTROL REGISTER
NO WRITE TO THE
FOR CHANNEL 1
1
REGISTER CHANNEL 5 SELECTED
DATA WRITTEN TO CONTROL
CONVERSION RESULT
FOR CHANNEL 1
16
IN2
) available for reading. The AD7298-1
1
16
CONVERSION RESULT
CONTROL REGISTER
NO WRITE TO THE
FOR CHANNEL 4
16