AD9467 Analog Devices, AD9467 Datasheet

no-image

AD9467

Manufacturer Part Number
AD9467
Description
16-Bit, 200 MSPS/250 MSPS Analog-to-Digital Converter
Manufacturer
Analog Devices
Datasheet

Specifications of AD9467

Resolution (bits)
16bit
# Chan
1
Sample Rate
250MSPS
Interface
LVDS,Par
Analog Input Type
Diff-Uni,SE-Uni
Ain Range
(2Vref) p-p,2 V p-p,2.5V p-p
Adc Architecture
Pipelined,Subranging
Pkg Type
CSP

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AD9467BCPZ-200
Manufacturer:
VISHAY
Quantity:
20 000
Part Number:
AD9467BCPZ-200
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Part Number:
AD9467BCPZ-250
Manufacturer:
AD
Quantity:
1 000
Part Number:
AD9467BCPZ-250
Manufacturer:
ADI
Quantity:
187
Part Number:
AD9467BCPZ-250
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Data Sheet
FEATURES
75.5 dBFS SNR to 210 MHz at 250 MSPS
90 dBFS SFDR to 300 MHz at 250 MSPS
SFDR at 170 MHz at 250 MSPS
60 fs rms jitter
Excellent linearity at 250 MSPS
2 V p-p to 2.5 V p-p (default) differential
Integrated input buffer
External reference support option
Clock duty cycle stabilizer
Output clock available
Serial port control
LVDS outputs (ANSI-644 compatible)
1.8 V and 3.3 V supply operation
APPLICATIONS
Multicarrier, multimode cellular receivers
Antenna array positioning
Power amplifier linearization
Broadband wireless
Radar
Infrared imaging
Communications instrumentation
GENERAL DESCRIPTION
The AD9467 is a 16-bit, monolithic, IF sampling analog-to-
digital converter (ADC). It is optimized for high performance
over wide bandwidths and ease of use. The product operates at
a 250 MSPS conversion rate and is designed for wireless
receivers, instrumentation, and test equipment that require a
high dynamic range.
The ADC requires 1.8 V and 3.3 V power supplies and a low
voltage differential input clock for full performance operation.
No external reference or driver components are required for
many applications. Data outputs are LVDS compatible (ANSI-644
compatible) and include the means to reduce the overall current
needed for short trace distances.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
92 dBFS at −1 dBFS
100 dBFS at −2 dBFS
full-scale input (programmable)
Selectable output data format
DNL = ±0.5 LSB typical
INL = ±3.5 LSB typical
Built-in selectable digital test pattern generation
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
CLK+
A data clock output (DCO) for capturing data on the output is
provided for signaling a new output bit.
The internal power-down feature supported via the SPI typically
consumes less than 5 mW when disabled.
Optional features allow users to implement various selectable
operating conditions, including input range, data format select,
and output data test patterns.
The AD9467 is available in a Pb-free, 72-lead, LFCSP specified
over the −40°C to +85°C industrial temperature range.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
6.
CLK–
VIN+
VIN–
16-Bit, 200 MSPS/250 MSPS
Analog-to-Digital Converter
IF optimization capability used to improve SFDR.
Outstanding SFDR performance for IF sampling
applications such as multicarrier, multimode 3G, and 4G
cellular base station receivers.
Ease of use: on-chip reference, high input impedance
buffer, adjustable analog input range, and an output clock
to simplify data capture.
Packaged in a Pb-free, 72-lead LFCSP package.
Clock duty cycle stabilizer (DCS) maintains overall ADC
performance over a wide range of input clock pulse widths.
Standard serial port interface (SPI) supports various
product features and functions, such as data formatting
(offset binary, twos complement, or Gray coding).
AGND
AD9467
MANAGEMENT
AND TIMING
BUFFER
FUNCTIONAL BLOCK DIAGRAM
CLOCK
AVDD1
©2010–2011 Analog Devices, Inc. All rights reserved.
AVDD2
AVDD3 SPIVDD
PIPELINE
Figure 1.
ADC
XVREF
REF
16
STAGING
OUTPUT
DRVDD DRGND
LVDS
AD9467
www.analog.com
16
2
2
CSB
SDIO
SCLK
OR+/OR–
D15+/D15–
TO
D0+/D0–
DCO+/DCO–

Related parts for AD9467

AD9467 Summary of contents

Page 1

... Optional features allow users to implement various selectable operating conditions, including input range, data format select, and output data test patterns. The AD9467 is available in a Pb-free, 72-lead, LFCSP specified over the −40°C to +85°C industrial temperature range. PRODUCT HIGHLIGHTS 1. ...

Page 2

... AD9467 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 AC Specifications.......................................................................... 4 Digital Specifications ................................................................... 6 Switching Specifications .............................................................. 7 Absolute Maximum Ratings............................................................ 8 Thermal Impedance ..................................................................... 8 ESD Caution.................................................................................. 8 Pin Configuration and Function Descriptions............................. 9 REVISION HISTORY 9/11—Rev Rev. C Changes to Figure 44 and Figure 45............................................. 17 3/11— ...

Page 3

... Full 485 536 580 Full Full Full Full 1.14 1.26 1.37 Full 4.4 90 Rev Page AD9467 AD9467BCPZ-250 Min Typ Max Unit 16 Bits Guaranteed −150 0 +150 LSB −3.5 −0.1 +2.5 %FSR −0.6 ±0.5 +1.3 LSB −11.8 ±3.5 +9.5 LSB ±0.023 %FSR/°C ±0.036 %FSR/° ...

Page 4

... Full 25°C 12.1/12.3 25°C 12.0/12.3 Full 25°C 12.0/12.2 25°C 11.9/12.0 2 25°C 95/95 25°C 86 95/95 Full 83 25°C 94/93 25°C 95/90 Full 25°C 93/88 25°C 92/86 Full 100/96 Full 100/98 Full 98/96 Full 96/93 Full 94/93 Full 90/89 Rev Page Data Sheet AD9467BCPZ-250 Max Min Typ Max 2.5 2/2.5 74.7/76.4 74.5/76.1 74.4/76.0 74.7 74.3/75.8 72.3 74.0/75.5 73.3/74.6 74.6/76.3 74.4/76.0 74.4/76.0 74.4 74.2/75.8 71.8 73.9/75.4 73.1/74.4 12.1/12.4 12.1/12.3 12.1/12.3 12.0/12.3 12.0/12.2 11.9/12.1 98/97 95/93 94/95 84 93/92 84 93/92 93/90 100/100 97/97 100/95 100/100 93/93 90/90 Unit V p-p ...

Page 5

... See the SFDR Optimization—Buffer Current Adjustment section for optimum settings. AD9467BCPZ-200 Temp Min Typ Max 25°C 96/98 25°C 86 97/97 Full 83 25°C 97/96 25°C 98/98 Full 25°C 96/97 25°C 95/95 25°C 95 25°C 93 Rev Page AD9467 AD9467BCPZ-250 Min Typ Max Unit 98/97 dBFS 97/93 dBFS dBFS 97/95 dBFS 90 97/93 dBFS 87 dBFS 97/95 dBFS 97/95 dBFS 97 dBFS 91 dBFS ...

Page 6

... Full 0.8 25°C 20 25°C 2.5 Full 1.2 3.6 Full 0.3 25°C 30 25°C 0.5 Full 1.7/3.1 Full 0.3 LVDS Full 247 545 Full 1.125 1.375 Offset binary Rev Page Data Sheet AD9467BCPZ-250 Min Typ Max Unit CMOS/LVDS/LVPECL 250 mV p-p 0 kΩ 2.5 pF 1.2 3 kΩ 0.5 pF 1.7/3.1 V 0.3 V LVDS 247 ...

Page 7

... Figure 2. 16-Bit Output Data Timing Rev Page AD9467BCPZ-250 Min Typ Max Unit 50 250 MSPS 200 ps 200 −200 +200 ps 100 ms 16 Clock cycles 1 rms 1 Clock cycles D15 D14 D15 D14 D15 D14 AD9467 ...

Page 8

... AD9467 ABSOLUTE MAXIMUM RATINGS Table 5. With Parameter Respect To Electrical AVDD1, AVDD3 AGND AVDD2, SPIVDD AGND DRVDD DRGND AGND DRGND AVDD2, SPIVDD AVDD1, AVDD3 AVDD1, AVDD3 DRVDD AVDD2, SPIVDD DRVDD Digital Outputs (Dx+, DRGND Dx−, OR+, OR−, DCO+, DCO−) CLK+, CLK− ...

Page 9

... D11 and D10 Digital Output True. D13−/D12− D13 and D12 Digital Output Complement. D13+/D12+ D13 and D12 Digital Output True. D15−/D14− D15 (MSB) and D14 Digital Output Complement. Rev Page AD9467 54 AVDD1 53 AVDD1 52 AVDD1 51 ...

Page 10

... AD9467 Pin No Mnemonic Description D15+/D14+ D15 (MSB) and D14 Digital Output True. DCO− Data Clock Digital Output Complement. DCO+ Data Clock Digital Output True. OR− Out-of-Range Digital Output Complement. OR+ Out-of-Range Digital Output True. ...

Page 11

... CLK– V Dx+ V Rev Page 345Ω SCLK, SDIO AND CSB 30kΩ Figure 7. Equivalent SCLK, SDIO, and CSB Input Circuit SPIVDD SDIO Figure 8. Equivalent SDIO Output Circuit 1kΩ XVREF 3pF Figure 9. Equivalent External VREF Input Circuit (When Enabled) AD9467 ...

Page 12

... AIN = –1.0dBFS SNR = 75.5dBFS –20 ENOB = 12.1 BITS SFDR = 90.0dBFS –40 –60 – FREQUENCY (MHz) = 210.3 MHz, 2.5 V p-p FS, AD9467-200 IN 0 AIN = –1.0dBFS SNR = 74.7dBFS –20 ENOB = 12.0 BITS SFDR = 86.5dBFS –40 –60 – FREQUENCY (MHz) = 290 ...

Page 13

... AIN = –1.0dBFS SNR = 75.5dBFS –20 ENOB = 12.1 BITS SFDR = 90.8dBFS –40 –60 –80 –100 –120 –140 FREQUENCY (MHz) = 210.3 MHz, 2.5 V p-p FS, AD9467-250 IN 0 AIN = –1.0dBFS SNR = 74.2dBFS –20 ENOB = 12.0 BITS SFDR = 91.0dBFS –40 –60 –80 –100 –120 –140 ...

Page 14

... SNR 75 SFDR 210 215 220 225 230 235 SAMPLE RATE (MSPS) Figure 23. SNR/SFDR vs 97.3 MHz, 2.5 V p-p FS, AD9467-250 SAMPLE IN 105 100 100 120 140 160 180 SAMPLE RATE (MSPS) Figure 24. SFDR vs 2.5 V p-p FS, AD9467-200 SAMPLE 110 105 ...

Page 15

... IMD3 = 95.9dBFS –40 –60 –80 –100 –120 –140 FREQUENCY (MHz) Figure 28. Two-Tone FFT with MHz and f IN1 2.5 V p-p FS, AD9467-200 0 AIN1 AND AIN2 = –7dBFS SFDR = 92.7dBFS –20 IMD2 = 98.2dBFS IMD3 = 92.7dBFS –40 –60 –80 –100 –120 –140 ...

Page 16

... MHz –2 –4 –6 –8 = 97.3 MHz, IN 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 Rev Page Data Sheet CODE Figure 37. DNL 4.3 MHz, 2.5 V p-p FS, AD9467-200 IN CODE Figure 38. INL 4.3 MHz, 2.5 V p-p FS, AD9467-250 IN CODE Figure 39. DNL 4.3 MHz, 2.5 V p-p FS, AD9467-250 IN ...

Page 17

... Figure 44. Input-Referred Noise Histogram, 2.5 V p-p FS, AD9467-200 140,000 120,000 100,000 200 250 300 Figure 45. Input-Referred Noise Histogram, 2.5 V p-p FS, AD9467-250 Rev Page –1 –2 –3 –3dB = 2.24GHz –4 –5 –6 –7 –8 –9 –10 1M 10M 100M 1G FREQUENCY (Hz) Figure 43 ...

Page 18

... AD9467 –55 –60 –65 AVDD2 –70 AVDD1 –75 –80 DRVDD –85 –90 ANALOG INPUT FREQUENCY (MHz) Figure 46. Power Supply Rejection (PSR), AD9467-250 100 100 150 BUFFER CURRENT PERCENTAGE (%) Figure 47. SFDR Performance vs. Buffer Current Percentage Over Analog Input Frequency, AD9467-200 Figure 48 ...

Page 19

... ADC. Maximum SNR performance is achieved by setting the ADC to the largest span in a differential configuration. In the default case of the AD9467, the largest input span available is 2.5 V p-p. For other input full-scale options, see the Full-Scale and Reference Options section. SFDR Optimization—Buffer Current Adjustment ...

Page 20

... IN Figure 53. Wideband Balun-Coupled Configuration for IF Applications Up Greater Than 100 MHz Differential Input Configurations There are several ways to drive the AD9467, either actively or passively; however, optimum performance is achieved by driving the analog input differentially. For applications where SNR and SFDR are key parameters, ...

Page 21

... RATIO 50Ω AC Figure 54. Wideband Differential Amplifier Input Configuration Using the Figure 55. Single-Tone FFT Performance Plot Using the ADL5562 Amplifier, Gain = 6 dB, and the AD9467-250 50Ω AC Figure 56. Wideband Differential VGA Input Configuration Using the Figure 57. Single-Tone FFT Performance Plot Using the ADL5201 VGA, Gain = 20 dB, and the AD9467-250 3.3V 40Ω ...

Page 22

... This signal is typically ac-coupled to the CLK+ and CLK− pins via a transformer or capacitors. These pins are biased internally and require no additional biasing. Figure 58 shows a preferred method for clocking the AD9467. The low jitter clock source is converted from a single-ended signal to a differential signal using an RF transformer. The back-to- back Schottky diodes across the secondary transformer limit clock excursions into the AD9467 to approximately 0 ...

Page 23

... Data Sheet Power Dissipation and Power-Down Mode As shown in Figure 62, the power dissipated by the AD9467 is proportional to its sample rate. The output power dissipation does not vary much because it is determined primarily by the DRVDD supply and bias current of the LVDS output drivers. 0.6 0.5 0.4 0.3 TOTAL POWER ...

Page 24

... An output clock is provided to assist in capturing data from the AD9467. Data is clocked out of the AD9467 and must be captured on the rising and falling edges of the DCO that supports double data rate (DDR) capturing. See the timing diagram shown in Figure 2 for more information. ...

Page 25

... Section 5.6 of the ITU-T 0.150 (05/96) standard. The only differences are that the starting value must be a specific value instead of all 1s (see Table 9 for the initial values) and the AD9467 inverts the bit stream with relation to the ITU standard. Table 9. PN Sequence Initial ...

Page 26

... SPI. The SDIO pin is bidirectional, functioning as an input during write phases and as an output during readback. If multiple SDIO pins share a common connection, care should be taken to ensure that proper V same load for each AD9467, Figure 67 shows the number of SDIO pins that can be connected together and the resulting V 1.80 1.79 1 ...

Page 27

... Minimum time for the SDIO pin to switch from an input to an output relative to the SCLK falling edge (not shown in Figure 68) Minimum time for the SDIO pin to switch from an output to an input relative to the SCLK rising edge (not shown in Figure 68) Rev Page DON’T CARE AD9467 DON’T CARE ...

Page 28

... Addresses that have values marked as 0 should be considered reserved and have a 0 written into their registers during power-up. DEFAULT VALUES When the AD9467 comes out of a reset, critical registers are preloaded with default values. These values are indicated in Table 13, where an X refers to an undefined feature. ...

Page 29

... 5-bit digital clock output delay adjustment 0 0000 0 0001 0 0010 0 0011 … 1 1111 Rev Page AD9467 Default (LSB) Value Default Notes/ Bit 1 Bit 0 (Hex) Comments Internal power- 0x00 Determines down mode various generic 00 = chip run modes of chip (default) operation ...

Page 30

... AD9467 Addr. (MSB) (Hex) Parameter Name Bit 7 Bit 6 18 vref analog_input Buffer Current Select 1 107 Buffer Current Select undefined feature, don’t write. Bit 5 Bit 4 Bit 3 Bit Input full-scale range adjust 0000 = 2.0 V p-p 0110 = 2.1 V p-p 0111 = 2.2 V p-p 1000 = 2.3 V p-p 1001 = 2.4 V p-p 1010 = 2.5 V p-p (default) ...

Page 31

... AD9467. An exposed continuous copper plane on the PCB should be con- nected to the AD9467 exposed paddle, Pin 0. The copper plane should have several vias to achieve the lowest possible resistive thermal path for heat dissipation to flow through the bottom of the PCB ...

Page 32

... REF 0.23 0.18 COMPLIANT TO JEDEC STANDARDS MO-220-VNND × Body, Very Thin Quad (CP-72-5) Dimensions shown in millimeters Package Description 72-Lead LFCSP_VQ 72-Lead LFCSP_VQ 72-Lead LFCSP_VQ 72-Lead LFCSP_VQ AD9467-200 Evaluation Board AD9467-250 Evaluation Board D09029-0-9/11(C) Rev Page 0.60 0.42 0.24 PIN 1 55 INDICATOR 72 1 EXPOSED PAD 8 ...

Related keywords