AD9641 Analog Devices, AD9641 Datasheet - Page 21

• Manufacturer Part Number: AD9641
• Description: 14-Bit, 80 MSPS/155 MSPS, 1.8 V Serial Output Analog-to-Digital Converter (ADC)
• Manufacturer: Analog Devices

Specifications of AD9641

• Resolution (bits): 14bit
• # Chan: 1
• Sample Rate: 80MSPS
• Interface: Ser
• Analog Input Type: Diff-Bip
• Ain Range: 1.75 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

Data Sheet
POWER DISSIPATION AND STANDBY MODE
As shown in Figure 60, the power dissipated by the
varies with its sample rate. The data in Figure 60 was taken
in JESD204A serial output mode, using the same operating
conditions as those used for the Typical Performance
Characteristics.
The
Bits[1:0] or by asserting the PDWN pin high. In this state, the
ADC typically dissipates 7 mW. During power-down, the output
drivers are placed in a high impedance state. Pulling the PDWN
pin low returns the
power dissipation in power-down mode is achieved by shutting
down the reference, reference buffer, biasing networks, and clock.
Internal capacitors are discharged when entering power-down
mode and then must be recharged when returning to normal
operation.
When using the SPI port interface, the user can place the ADC
in power-down mode or standby mode (Register 0x08, Bits[1:0]).
Standby mode allows the user to keep the internal reference
circuitry powered and the JESD204A outputs running when
faster wake-up times are required.
Table 10.
Configuration
One Converter
One JESD204A Link
One Lane Per Link
0.30
0.20
0.10
AD9641
0
40
AD9641
Figure 60. Power and Current vs. Encode Frequency
I
DRVDD
is placed in power-down mode using Register 0x08,
50
JESD204A Typical Configuration
AD9641
ENCODE FREQUENCY (MSPS)
POWER
TOTAL
to its normal operating mode. Low
60
I
AVDD
70
JESD204A Link Settings
M = 1; L = 1; S = 1; F = 2
N’ = 16; CF = 0
CS = 0, 1, 2; K = N/A
SCR = 0, 1; HD = 0
AD9641
80
0.15
0.10
0.05
0
Rev. B | Page 21 of 36
DIGITAL OUTPUTS
JESD204A Transmit Top Level Description
The
No. 204A (JESD204A), which describes a serial interface for
data converters. JESD204A uses 8b/10b encoding, as well as
optional scrambling. K28.5 and K28.7 comma symbols are used
for frame synchronization, and the K28.3 control symbol is used
for lane synchronization. The receiver is required to lock onto
the serial data stream and recover the clock with the use of a PLL.
For details on the output interface, users are encouraged to refer
to the JESD204A standard.
The JESD204A link is described according to the following
nomenclature:














The JESD204A block for the
configurations described in Table 10.
AD9641
S = samples transmitted per single converter per
frame cycle
M = number of converters per converter device (link)
L = number of lanes per converter device (link)
N = converter resolution
N’ = total number of bits per sample
CF = number of control words per frame clock cycle per
converter device (link)
CS = number of control bits per conversion sample
K = number of frames per multiframe
HD = high density mode
F = number of octets per frame
C = control bit (overrange, overflow, underflow)
T = tail bit
SCR = scrambling enabled
FCHK = checksum
digital output complies with the JEDEC Standard
Comments
Maximum sample rate = 80 or 155 MSPS
AD9641
is designed to support the
AD9641