AD9641 Analog Devices, AD9641 Datasheet - Page 26

• Manufacturer Part Number: AD9641
• Description: 14-Bit, 80 MSPS/155 MSPS, 1.8 V Serial Output Analog-to-Digital Converter (ADC)
• Manufacturer: Analog Devices

Specifications of AD9641

• Resolution (bits): 14bit
• # Chan: 1
• Sample Rate: 80MSPS
• Interface: Ser
• Analog Input Type: Diff-Bip
• Ain Range: 1.75 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

AD9641
There are nine digital output test pattern options available that
can be initiated through the SPI (see Table 14 for the output bit
sequencing options). This feature is useful when validating
receiver capture and timing. Some test patterns have two serial
sequential words and can be alternated in various ways, depending
on the test pattern selected. Note that some patterns do not
adhere to the data format select option. In addition, custom
user-defined test patterns can be assigned in the user pattern
registers (Address 0x19 and Address 0x20).
The PN sequence short pattern produces a pseudorandom bit
sequence that repeats itself every 2
of the PN sequence short and how it is generated can be found
in Section 5.1 of the ITU-T O.150 (05/96) recommendation.
The only difference is that the starting value must be a specific
value instead of all 1s (see Table 13 for the initial values).
The PN sequence long pattern produces a pseudorandom bit
sequence that repeats itself every 2
Table 14. Flexible Output Test Modes from SPI Register 0x0D
Output Test Mode
Bit Sequence
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001 to 1110
1111
Pattern Name
Off (default)
Midscale short
+Full-scale short
−Full-scale short
Checkerboard
PN sequence long
PN sequence short
One-/zero-word toggle
User test mode
Not used
Ramp output
9
23
− 1 (511) bits. A description
− 1 (8,388,607) bits.
Digital Output Word 1 (Default
Twos Complement Format)
Not applicable
00 0000 0000 0000
01 1111 1111 1111
10 0000 0000 0000
10 1010 1010 1010
Not applicable
Not applicable
1111 1111 1111
User data from Register 0x19 to
Register 0x20
Not applicable
N
Rev. B | Page 26 of 36
A description of the PN sequence long and how it is generated
can be found in Section 5.6 of the ITU-T O.150 (05/96) standard.
The only differences are that the starting value must be a specific
value instead of all 1s (see Table 13 for the initial values) and
that the
standard.
Table 13. PN Sequence
Sequence
PN Sequence Short
PN Sequence Long
Register 0x62 allows patterns that are similar to those described
in Table 14 to be input at different points along the datapath.
This allows the user to provide predictable output data on the
serial link without it having been manipulated by the internal
formatting logic. Refer to Table 17 for additional information
on the test modes available in Register 0x62.
AD9641
Digital Output Word 2 (Default
Twos Complement Format)
Not applicable
Same
Same
Same
01 0101 0101 0101
Not applicable
Not applicable
0000 0000 0000
User data from Register 0x19 to
Register 0x20
Not applicable
N + 1
inverts the bit stream with relation to the ITU-T
Initial
Value
0x0092
0x3AFF
First Three Output Samples
(MSB First)
0x125B, 0x3C9A, 0x2660
0x3FD7, 0x0002, 0x36E0
Data Sheet
Subject to Data
Format Select
Yes
Yes
Yes
Yes
No
Yes
Yes
No
Yes
No