AD7606 Analog Devices, AD7606 Datasheet
AD7606
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AD7606 Summary of contents
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... One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 Single- True Number of Ended Differential Simultaneous Inputs Inputs Sampling Channels AD7608 AD7609 8 AD7606 8 AD7606-6 6 AD7606-4 4 AD7607 8 REFCAPB REFCAPA REFIN/REFOUT REF SELECT 2.5V REF AGND OUT SERIAL D B OUT ...
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... AD7606/AD7606-6/AD7606-4 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 General Description ......................................................................... 3 Specifications ..................................................................................... 4 Timing Specifications .................................................................. 7 Absolute Maximum Ratings .......................................................... 11 Thermal Resistance .................................................................... 11 ESD Caution ................................................................................ 11 Pin Configurations and Function Descriptions ......................... 12 Typical Performance Characteristics ........................................... 17 Terminology .................................................................................... 21 Theory of Operation ...................................................................... 22 Converter Details........................................................................ 22 REVISION HISTORY 1/12—Rev Rev. C Changes to Analog Input Ranges Section ................................... 22 10/11— ...
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... The input clamp protection circuitry can tolerate voltages up to ±16.5 V. The AD7606 has 1 MΩ analog input impedance regardless of sampling frequency. The single supply operation, on-chip filtering, and high input impedance eliminate the need for driver op amps and external bipolar supplies ...
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... AD7606/AD7606-6/AD7606-4 SPECIFICATIONS V = 2.5 V external/internal 4. 5. REF CC Table 2. Parameter DYNAMIC PERFORMANCE Signal-to-Noise Ratio (SNR Signal-to-(Noise + Distortion) (SINAD) Dynamic Range Total Harmonic Distortion (THD) 2 Peak Harmonic or Spurious Noise (SFDR) Intermodulation Distortion (IMD) 2 Second-Order Terms Third-Order Terms Channel-to-Channel Isolation ...
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... SINK Twos complement All eight channels included; see Table 3 Per channel, all eight channels included Digital inputs = DRIVE AD7606 AD7606-6 AD7606 200 kSPS SAMPLE AD7606 AD7606-6 AD7606-4 Rev Page AD7606/AD7606-6/AD7606-4 Min Typ Max Unit ±10 V ±5 V 5.4 µA 2.5 µ ...
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... Normal Mode (Operational) 8 Standby Mode Shutdown Mode Temperature range for the B version is −40°C to +85°C. The AD7606 is operational up to 125°C with throughput rates ≤ 160 kSPS, and the SNR typically reduces 125°C. 2 See the Terminology section. ...
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... Oversampling off; AD7606-6 µs Oversampling off; AD7606-4 µs Oversampling by 2; AD7606 µs Oversampling by 4; AD7606 µs Oversampling by 8; AD7606 µs Oversampling by 16; AD7606 µs Oversampling by 32; AD7606 µs Oversampling by 64; AD7606 µs STBY rising edge to CONVST x rising edge; power-up time from standby mode ms STBY rising edge to CONVST x rising edge ...
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... AD7606/AD7606-6/AD7606-4 Limit at T (0.1 × V 0.9 × V Logic Input Levels) Parameter Min SERIAL READ OPERATION f SCLK 0 SCLK t 0 SCLK FRSTDATA OPERATION Limit MIN MAX MIN MAX and (0.3 × ...
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... SCLK falling edge to FRSTDATA low 3 5.25V DRIVE 2 2.7V DRIVE ns Delay from CS rising edge until FRSTDATA three- state enabled = 5 ns (10 and timed from a voltage level of 1 DRIVE ) + ((N − 1) × 1 µs)). N is the oversampling ratio. For the AD7606-6, CONV ...
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... AD7606/AD7606-6/AD7606 DATA: INVALID DB[15: FRSTDATA CS AND RD DATA: DB[15:0] FRSTDATA CS SCLK OUT D B OUT FRSTDATA CS RD DATA: DB[7:0] FRSTDATA Figure 4. Parallel Mode, Separate CS and RD Pulses Figure 5. CS and RD , Linked Parallel Mode ...
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... Package Type −0 0.3 V DRIVE 64-Lead LQFP −0 0 ±10 mA ESD CAUTION −40°C to +85°C −65°C to +150°C 150°C 240 (+0)°C 260 (+0)° Rev Page AD7606/AD7606-6/AD7606-4 θ θ Unit °C/W ...
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... TOP VIEW (Not to Scale) RANGE 8 9 CONVST A CONVST B 10 RESET 11 RD/SCLK BUSY 14 FRSTDATA 15 DB0 Figure 9. AD7606-6 Pin Configuration Rev Page Data Sheet AGND 47 46 REFGND REFCAPB 45 REFCAPA 44 REFGND 43 REFIN/REFOUT 42 AGND 41 AGND ...
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... DB[7:0] transfer the 16-bit conversion results in two RD operations, with DB0 as the LSB of the data transfers. STBY Standby Mode Input. This pin is used to place the AD7606/AD7606-6/ AD7606-4 into one of two power-down modes: standby mode or shutdown mode. The power-down mode entered depends on the state of the RANGE pin, as shown in Table 7 ...
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... V2 for the AD7606-4. CONVST B can be used to initiate simultaneous sampling on the other analog inputs: V5, V6, V7, and V8 for the AD7606; V4, V5, and V6 for the AD7606-6; and V3 and V4 for the AD7606-4. This is possible only when oversampling is not switched on. When the CONVST A or CONVST B pin transitions from low to high, the front-end track-and-hold circuitry for the respective analog inputs is set to hold ...
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... Table 8). When PAR/SER/BYTE SEL = 1 and DB15/BYTE SEL = 0, the AD7606 operates in serial interface mode. When PAR/SER/BYTE SEL = 1 and DB15/BYTE SEL = 1, the AD7606 operates in parallel byte interface mode. REF SELECT Internal/External Reference Selection Input. Logic input. If this pin is set to logic high, the internal reference is selected and enabled ...
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... Analog Input 3. For the AD7606-4, this is an AGND pin. AGND Analog Input Ground Pin. For the AD7606-4, this is an AGND pin. AGND Analog Input 4. For the AD7606-6 and the AD7606-4, this is an AGND pin. AGND Analog Input Ground Pin. For the AD7606-6 and AD7606-4, this is an AGND pin. ...
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... AD7606/AD7606-6/AD7606-4 2 SAMPLE 1 25°C A INTERNAL REFERENCE ±10V RANGE 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0 10k 20k 30k 40k CODE Figure 14. AD7606 Typical INL, ±10 V Range 1 DRIVE F SAMPLE 0 25°C A INTERNAL REFERENCE 0.6 ±10V RANGE 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 10k 20k ...
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... AD7606/AD7606-6/AD7606-4 1.00 AV INTERNAL REFERENCE 0.75 ±5V RANGE F T 0.50 0.25 0 –0.25 –0.50 –0.75 –1.00 0 8192 16,384 24,576 32,768 40,960 CODE Figure 17. AD7606 Typical DNL, ±5 V Range –5 –10 200kSPS –15 AV EXTERNAL REFERENCE –20 –40 –25 – TEMPERATURE (°C) Figure 18. NFS Error vs. Temperature 20 ...
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... INTERNAL REFERENCE NO OS ±10V RANGE 80 10 100 1k 10k INPUT FREQUENCY (Hz) – DRIVE INTERNAL REFERENCE –60 AD7606 RECOMMENDED DECOUPLING USED F = 150kSPS SAMPLE – 25°C A INTERFERER ON ALL UNSELECTED CHANNELS –80 –90 ±10V RANGE –100 ±5V RANGE –110 –120 –130 –140 ...
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... VARIES WITH OS RATE SAMPLE 8 OS2 OS4 OS8 OS16 OS32 OVERSAMPLING RATIO Figure 32. Supply Current vs. Oversampling Rate ±10V RANGE ±5V RANGE DRIVE INTERNAL REFERENCE AD7606 RECOMMENDED DECOUPLING USED F = 200kSPS SAMPLE T = 25° 100 200 300 400 500 600 700 800 900 AV ...
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... N-bit converter with a sine wave input is given by Signal-to-(Noise + Distortion) = (6. 1.76) dB Thus, for a 16-bit converter, the signal-to-(noise + distortion dB. AD7606/AD7606-6/AD7606-4 Total Harmonic Distortion (THD) The ratio of the rms sum of the harmonics to the fundamental. For the AD7606/AD7606-6/AD7606- defined as THD (dB) = ...
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... The analog inputs on the AD7606/AD7606-6/AD7606-4 can accept true bipolar input signals. The RANGE pin is used to select either ± ± the input range. The AD7606/ AD7606-6/AD7606-4 operate from a single 5 V supply. The AD7606/AD7606-6/AD7606-4 contain input clamp ...
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... The conversion clock for the part is internally generated, and the conversion time for all channels is 4 μs on the AD7606, 3 μs on the AD7606-6, and 2 μs on the AD7606-4. On the AD7606, the BUSY signal returns low after all eight conversions to indicate the end of the conversion process. On the falling edge of BUSY, the track-and-hold amplifiers return to track mode ...
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... External Reference Mode One ADR421 external reference can be used to drive the REFIN/REFOUT pins of all AD7606 devices (see Figure 41). In this configuration, each REFIN/REFOUT pin of the AD7606/AD7606-6/AD7606-4 should be decoupled with at least a 100 nF decoupling capacitor. ...
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... Data Sheet TYPICAL CONNECTION DIAGRAM Figure 43 shows the typical connection diagram for the AD7606/ AD7606-6/AD7606-4. There are four AV part, and each of the four pins should be decoupled using a 100 nF capacitor at each supply pin and a 10 µF capacitor at the supply source. The AD7606/AD7606-6/AD7606-4 can operate with the internal reference or an externally applied reference ...
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... BUSY CS/RD DATA: DB[15:0] FRSTDATA Figure 44. AD7606 Simultaneous Sampling on Channel Sets While Using Independent CONVST A and CONVST B Signals—Parallel Mode transformers system, this allows for up to 9° of phase compensation; and system, it allows for up to 10° of phase compensation. This is accomplished by pulsing the two CONVST pins independently and is possible only if oversampling is not in use ...
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... Channel V1. The next RD falling edge updates the bus with the V2 conversion result, and so on. On the AD7606, the eighth falling edge of RD clocks out the conversion result for Channel V8. When the RD signal is logic low, it enables the data conversion result from each channel to be transferred to the digital host (DSP, FPGA) ...
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... used as a single D OUT the channel results are output in the following order: V4, V5, V6, V1, V2, and V3 for the AD7606-6; and V3, V4, V1, and V2 for the AD7606-4. Figure 6 shows the timing diagram for reading one channel of data, framed by the CS signal, from the AD7606/AD7606-6/ AD7606-4 in serial mode ...
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... AND CONV 19µs 9µs 4µ BUSY Figure 47. AD7606—No Oversampling, Oversampling × 2, and Oversampling × 4 While Using Read After Conversion CONVERSION Maximum Throughput Range (kHz) CONVST Frequency (kHz) 22 200 22 100 18 ...
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... AD7606/AD7606-6/AD7606-4 Figure 49 to Figure 55 illustrate the effect of oversampling on the code spread histogram plot. As the oversample rate is increased, the spread of the codes is reduced. 1000 NO OVERSAMPLING 928 887 F = 200kSPS 900 SAMPLE 2.5V DRIVE 800 700 600 500 400 300 200 ...
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... Data Sheet When the oversampling mode is selected for the AD7606/ AD7606-6/AD7606-4, it has the effect of adding a digital filter function after the ADC. The different oversampling rates and the CONVST sampling frequency produce different digital filter frequency profiles. Figure 56 to Figure 61 show the digital filter frequency profiles for the different oversampling rates ...
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... REFIN/REFOUT pin and the REFCAPA and REFCAPB pins as close as possible to their respective AD7606/ AD7606-6/AD7606-4 pins; and, where possible, they should be placed on the same side of the board as the AD7606 device. Figure 62 shows the recommended decoupling on the top layer of the AD7606 board. Figure 63 shows bottom layer decoupling, ...
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... Figure 64. AD7606/AD7606-6/AD7606-4 Figure 64. Layout for Multiple AD7606 Devices—Top Layer and Supply Plane Layer Rev Page AVCC AVCC ...
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... Z = RoHS Compliant Part. 2 The EVAL-AD7606EDZ, EVAL-AD7606-6EDZ, and EVAL-AD7606-4EDZ can be used as standalone evaluation boards or in conjunction with the CED1Z for evaluation/demonstration purposes. 3 The CED1Z allows the PC to control and communicate with all Analog Devices, Inc., evaluation boards ending in the EDZ designator. ...
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... Data Sheet NOTES AD7606/AD7606-6/AD7606-4 Rev Page ...
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... AD7606/AD7606-6/AD7606-4 NOTES ©2010–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08479-0-1/12(C) Rev Page Data Sheet ...