AD9644 Analog Devices, AD9644 Datasheet - Page 26

• Manufacturer Part Number: AD9644
• Description: 14-Bit, 80 MSPS/155 MSPS, 1.8V Dual, Serial Output A/D Converter
• Manufacturer: Analog Devices

Specifications of AD9644

• Resolution (bits): 14bit
• # Chan: 2
• Sample Rate: 155MSPS
• Analog Input Type: Diff-Bip
• Ain Range: 1.75 V p-p
• Adc Architecture: Pipelined

AD9644
Table 10. AD9644 JESD204A Typical Configurations
AD9644 Configuration
Two Converters
Two JESD204A Links
One Lane Per Link
Two Converters
One JESD204A Link
Two Lanes Per Link
Two Converters
One JESD204A Link
One Lane Per Link
Initial Frame Synchronization
The serial interface must synchronize to the frame boundaries
before data can be properly decoded. The JESD204A standard
has a synchronization routine to identify the frame boundary.
When the DSYNC pin is taken low for at least two clock cycles,
the AD9644 enters the code group synchronization mode. The
AD9644 transmits the K28.5 comma symbol until the receiver
achieves synchronization. The receiver should then deassert the
sync signal (take DSYNC high) and the AD9644 begins the
initial lane alignment sequence (when enabled through Bits[3:2]
of Address 0x60) and subsequently begins transmitting sample
data. The first non-K28.5 symbol corresponds to the first octet
in a frame.
TIME
TRANSMITTER
JESK204A Link A Settings
M = 1; L = 1; S = 1; F = 2
N’ = 16; CF = 0
CS = 0, 1, 2; K = N/A
SCR = 0, 1; HD = 0
M = 2; L = 2; S = 1; F = 2
N’ = 16
CF = 0; CS = 0, 1, 2
K = 16; SCR = 0, 1;
HD = 0
M = 2; L = 1; S = 1; F = 4
N’ = 16
CF = 0; CS = 0, 1, 2
K = 8; SCR = 0, 1; HD = 0
DATA
FROM
ADC
FROM
WORD 1[5:0], TAIL BITS[1:0]
WORD 0[5:0],TAIL BITS[1:0]
WORD 0[13:6]
WORD 1[13:6]
DECODER
Figure 64. AD9644 14-Bit Data Transmission with Tail Bits
(ADD TAIL BITS)
8B/10B
ASSEMBLER
FRAME
Figure 63. AD9644 ADC Output Data Path
Figure 65. Required Receiver Data Path
JESD204A Link B Settings
M = 1; L = 1; S = 1; F = 2
N’ = 16; CF = 0
CS = 0, 1, 2; K = N/A
SCR = 0, 1; HD = 0
Disabled
Disabled
Rev. C | Page 26 of 44
DESCRAMBLER
1 + x
OPTIONAL
SCRAMBLER
1 + x
OPTIONAL
14
+ x
14
15
+ x
15
The DSYNC input can be driven either from a differential
LVDS source or by using a single-ended CMOS driver circuit.
The DSYNC input default to LVDS mode but can be set to
CMOS mode by setting Bit 4 in SPI Address 0x61. If it is driven
differentially from an LVDS source, then an external 100 Ω
termination resistor should be provided. If the DSYNC input is
driven single-ended then the CMOS signal should be connected
to the DSYNC+ signal and the DSYNC− signal should be left
disconnected.
SYMBOL 0[9:0]
SYMBOL 1[9:0]
SYMBOL 2[9:0]
SYMBOL 3[9:0]
ALIGNMENT
FRAME
ENCODER
8B/10B
Comments
Maximum sample rate = 80 MSPS or 155 MSPS
Maximum sample rate = 80 MSPS or 155 MSPS
Required for applications needing two aligned
samples (I/Q applications)
Maximum sample rate = 80 MSPS
TO
RECEIVER
DATA
OUT
FRAME 0
FRAME 1
Data Sheet