AD9644 Analog Devices, AD9644 Datasheet - Page 28

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AD9644

Manufacturer Part Number
AD9644
Description
14-Bit, 80 MSPS/155 MSPS, 1.8V Dual, Serial Output A/D Converter
Manufacturer
Analog Devices
Datasheet

Specifications of AD9644

Resolution (bits)
14bit
# Chan
2
Sample Rate
155MSPS
Analog Input Type
Diff-Bip
Ain Range
1.75 V p-p
Adc Architecture
Pipelined
AD9644
Figure 68 and Figure 69 shows an example of the digital output
(default) data eye and a time interval error (TIE) jitter histogram.
Additional SPI options allow the user to further increase the
output driver voltage swing of all four outputs to drive longer
trace lengths (see Address 0x15 in Table 17). Even though this
produces sharper rise and fall times on the data edges and is less
prone to bit errors, the power dissipation of the DRVDD supply
increases when this option is used. See the Memory Map section
for more details.
The format of the output data is twos complement by default.
Table 12 provides an example of this output coding format.
To change the output data format to offset binary or gray code,
see the Memory Map section (Address 0x14 in Table 17).
–200
–400
–100
–200
–300
–400
–500
400
200
500
400
300
200
100
0
0
–600
–300
EYE: TRANSITION BITS
OFFSET: –0.004
ULS: 8000; 639999, TOTAL: 8000; 639999
EYE: TRANSITION BITS
OFFSET: –0.004
ULS: 8000; 124,0001, TOTAL: 8000; 124,0001
–400
–200
HEIGHT1: EYE DIAGRAM
HEIGHT1: EYE DIAGRAM
–200
–100
TIME (ps)
TIME (ps)
Figure 69. AD9644-155 Digital Outputs Data Eye, Histogram and Bathtub, External 100 Ω Terminations
Figure 68. AD9644-80 Digital Outputs Data Eye, Histogram and Bathtub, External 100 Ω Terminations
0
0
200
100
400
200
600
300
1
1
25,000
20,000
15,000
10,000
50,000
45,000
40,000
35,000
30,000
25,000
20,000
15,000
10,000
5000
5000
0
0
610
305
310
615
Rev. C | Page 28 of 44
PERIOD1: HISTOGRAM
PERIOD1: HISTOGRAM
315
620
TIME (ps)
TIME (ps)
320 325
625
630
Table 12. Digital Output Coding
Code
8191
0
−1
−8192
The lowest typical clock rate is 40 MSPS. For clock rates slower
than 60 MSPS, the user should set Bit 3 to 0 in the serial control
register (Address 0x21 in Table 17). This option sets the PLL
loop bandwidth to use clock rates between 40 MSPS and
60 MSPS.
Setting Bit 2 in the output mode register (Address 0x14) allows
the user to invert the digital samples from their nominal state.
As shown in Figure 64, the MSB is transmitted first in the data
output serial stream.
330 335
635
(VIN+ ) − (VIN− ),
Input Span = 1.75 V p-p (V)
+0.875
0.00
−0.000107
−0.875
+
4
4
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
–10
–12
–14
–10
–12
–14
–2
–4
–6
–8
–0.5
–2
–4
–6
–8
–0.5
0
0
WIDTH@BER1: BATHTUB
WIDTH@BER1: BATHTUB
0.781
0.742
ULS
ULS
0
0
Digital Output
Twos Complement
([D13:D0])
01 1111 1111 1111
00 0000 0000 0000
11 1111 1111 1111
10 0000 0000 0000
Data Sheet
0.5
0.5
+
3
3

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