AD9963 Analog Devices, AD9963 Datasheet - Page 11

• Manufacturer Part Number: AD9963
• Description: 10-/12-Bit, Low Power, Broadband MxFE
• Manufacturer: Analog Devices

Specifications of AD9963

• Resolution (bits): 12bit
• Throughput Rate: 100MSPS
• # Chan: 2
• Supply V: Multi(+1.8Anlg, +1.8Dig),Multi(+1.8Anlg, +3.3Dig) ,Single(+1.8),Single(+3.3)
• Sample Rate: 100MSPS
• Adc Bits X #adcs-speed: 12x2-100 MHz
• Dac Bits X #dacs-clkspeed: 12x2-170 MHz
• Pkg Type: CSP
• Primary Application: Broadband Wireless

Table 9. AD9963 Pin Function Descriptions
Pin No.
1
2
3, 4
5, 11
6
7
8
9
10
12, 13
14
15
16
17
18
19, 34
20, 33, 51
21 to 32
35
36
37
38
39 to 50
52
53
Mnemonic
AUX33V
AUXADCREF
RXQP, RXQN
RXGND
RXBIAS
RX18V
RX33V
RX18VF
RXCML
RXIN, RXIP
LDO_EN
RESET
SCLK
CS
SDIO
DGND
DRVDD
TRXD11 to TRXD0
TRXIQ
TRXCLK
TXCLK
TXIQ/TXnRX
TXD11 to TXD0
DVDD18
DLL18V
Description
Analog Supply for the Auxiliary ADC and Auxiliary DACs (3.3 V ± 10%, 1.8 V ± 10% If Auxiliary ADC Is
Powered Down).
Reference Output (or input) for Auxiliary ADC.
Differential ADC Q Inputs. Full-scale input voltage range is 1.56 V p-p differential.
Receive Path Ground.
External Bias Resistor Connection. This voltage is nominally 0.5 V. A 10 kΩ resistor can be connected
between this pin and analog ground to improve the Rx ADC full-scale accuracy.
Output of RX18V Voltage Regulator.
Input to RX18V and RX18VF Voltage Regulators (2.5 V to 3.3 V). If LDOs are not being used, short Pin 8 to
Pin 7.
Output of RX18VF Voltage Regulator.
ADC Common-Mode Voltage Output.
Differential ADC I Inputs. Full-scale input voltage range is 1.56 V p-p differential.
Control pin for LDOs (GND = Disable all LDOs, Float = Enable DVDD18 LDO Only, DRVDD = Enable All
LDOs).
Reset. Active low to reset the configuration registers to default values and reset device.
Clock Input for Serial Port.
Active Low Chip Select.
Bidirectional Data Line for Serial Port.
Digital Core Ground.
Input/Output Pad Ring Supply Voltage (1.8 V to 3.3 V).
ADC Output Data in Full Duplex Mode. ADC output data and DAC input data in half-duplex mode.
Output Signal Indicating from Which ADC the Output Data Is Sourced.
Qualifying Clock for the TRXD Bus.
Qualifying Clock for the TXD Bus. It can be configured as either an input or output.
Dual Function Pin. In half-duplex mode (TXnRX), this pin controls the direction of the TRX port. In full-
duplex mode (TXIQ), this input signal indicates to which DAC, I or Q, the TxDAC Input Data is intended.
TxDAC Input Data.
Digital Core 1.8 V Supply.
Output of DLL18V Voltage Regulator.
AUXADCREF
NOTES
1. EXPOSED PAD MUST BE SOLDERED TO PCB.
LDO_EN
AUX33V
RXBIAS
RX18VF
RXGND
RXGND
RXCML
RESET
RX18V
RX33V
RXQN
RXQP
SCLK
RXIN
SDIO
RXIP
CS
10
11
12
13
14
15
16
17
18
1
2
3
4
5
6
7
8
9
Figure 3. AD9963 Pin Configuration
PIN 1
INDICATOR
Rev. 0 | Page 11 of 60
(TOP VIEW)
AD9963
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
DLLFILT
DLL18V
DVDD18
DRVDD
TXD0
TXD1
TXD2
TXD3
TXD4
TXD5
TXD6
TXD7
TXD8
TXD9
TXD10
TXD11
TXIQ/TXnRX
TXCLK
AD9961/AD9963