AD9963 Analog Devices, AD9963 Datasheet - Page 21

• Manufacturer Part Number: AD9963
• Description: 10-/12-Bit, Low Power, Broadband MxFE
• Manufacturer: Analog Devices

Specifications of AD9963

• Resolution (bits): 12bit
• Throughput Rate: 100MSPS
• # Chan: 2
• Supply V: Multi(+1.8Anlg, +1.8Dig),Multi(+1.8Anlg, +3.3Dig) ,Single(+1.8),Single(+3.3)
• Sample Rate: 100MSPS
• Adc Bits X #adcs-speed: 12x2-100 MHz
• Dac Bits X #dacs-clkspeed: 12x2-170 MHz
• Pkg Type: CSP
• Primary Application: Broadband Wireless

When LSB first is set by Register 0x00, Bit 2 and Register 0x00,
Bit 6, it takes effect immediately. In multibyte transfers,
subsequent bytes reflect any changes in the serial port
configuration. To avoid problems reconfiguring the serial port
operation, any data written to 0x00 must be mirrored (the eight
bits should read the same, forward or backward). Mirroring the
data makes it irrelevant whether LSB first or MSB first is in
effect. As an example of this mirroring, the default setting for
Register 0x00 is 00011000.
Ending Transfers
When the transfer is 1, 2, or 3 bytes, the data transfer ends after
the required number of clock cycles have been received. CS can
be raised after each sequence of eight bits to stall the bus (except
after the last byte, where it ends the cycle). When the bus is
stalled, the serial transfer resumes when CS is lowered. Raising
CS on a non byte boundary resets the serial control port.
The AD9961/AD9963 serial control port register addresses
decrement from the register address just written toward 0x00
for multibyte I/O operations if the MSB first mode is active
(default). If the LSB first mode is active, the register address of
the serial control port increments from the address just written
toward 0xFF for multibyte I/O operations.
Streaming mode transfers always terminate when
Streaming mode transfers also terminate whenever the address
reaches 0xFF. Note that unused addresses are not skipped
during multibyte I/O operations. To avoid unpredictable device
behavior, do not write to reserved registers.
Table 12. Serial Control Port, 16-Bit Instruction Word, MSB First
MSB
I15
R/W
SCLK
SDIO
CS
SCLK
SDIO
DON’T CARE
CS
DON’T CARE
I14
N1
DON’T CARE
DON’T CARE
R/W
I13
N0
N1
N0
t
S
R/W
I12
0
A12
t
A11 A10 A9
Figure 35. Serial Control Port Write—MSB First, 16-Bit Instruction, Timing Measurements
DS
16-BIT INSTRUCTION HEADER
N1
Figure 34. Serial Control Port Access—MSB First, 16-Bit Instruction, 2-Byte Data
I11
0
N0
t
DH
A8
A12
A7
I10
0
t
LOW
A6
CS is raised.
A11
A5
I9
0
A4
A10
t
HIGH
A3
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A2
A9
I8
0
t
CLK
A1
A8
A0
I7
A7
D7 D6
A7
Table 11. Streaming Mode (No Addresses Are Skipped)
Write Mode
LSB First
MSB First
SUB SERIAL INTERFACE COMMUNICATIONS
The AD9963/AD9961 have two registers that require a different
communication sequence. These registers are 0x0F and 0x10.
The write sequence for these two registers requires a write to
Register 0x05, a write to the Register (0x0F or 0x10), and then a
write to Register 0xFF. The write takes effect when the write to
Register 0xFF is completed.
For example, to enable the RXCML pin output buffer, the
register write sequence is:
1.
2.
3.
4.
An example of updating Register 0x10 is given in the ADC
Digital Offset Adjustment section.
REGISTER (N) DATA
D5
A6
Write 0x03 into Register 0x05. This addresses both of the
Rx ADCs.
Write 0x02 into Register 0x0F. This sets the RXCML
enable bit.
Write 0x01 into Register 0xFF. This updates the internal
register, which activates the RXCML buffer.
Write 0x00 into Register 0x05. This returns the SPI to the
normal addressing mode.
I6
A6
D4
A5
D3
D2
I5
A5
D4
D1
Address Direction
Increment
Decrement
D0
D3
I4
A4
D7
REGISTER (N – 1) DATA
D6
D2
D5
I3
A3
D1
D4
D3
D0
AD9961/AD9963
D2
I2
A2
t
C
Stop Sequence
0xFD, 0xFE, 0xFF, stop
0x01, 0x00, 0xFF, stop
D1
DON’T CARE
DON’T CARE
D0
I1
A1
DON’T CARE
DON’T CARE
LSB
I0
A0