AD9963 Analog Devices, AD9963 Datasheet - Page 48

• Manufacturer Part Number: AD9963
• Description: 10-/12-Bit, Low Power, Broadband MxFE
• Manufacturer: Analog Devices

Specifications of AD9963

• Resolution (bits): 12bit
• Throughput Rate: 100MSPS
• # Chan: 2
• Supply V: Multi(+1.8Anlg, +1.8Dig),Multi(+1.8Anlg, +3.3Dig) ,Single(+1.8),Single(+3.3)
• Sample Rate: 100MSPS
• Adc Bits X #adcs-speed: 12x2-100 MHz
• Dac Bits X #dacs-clkspeed: 12x2-170 MHz
• Pkg Type: CSP
• Primary Application: Broadband Wireless

AD9961/AD9963
DIGITAL INTERFACES
The AD9961/AD9963 have two parallel interface ports, the
Tx port and the TRx port. The operation of the ports depends
on whether the device is configured for full-duplex or half-
duplex mode.
In full-duplex mode, the TRx and Tx port operate independently.
The TRx port outputs samples from the receive path and the Tx
port accepts incoming samples for the transmit port.
In half-duplex mode, the TRx port outputs samples from the
receive path and accepts incoming samples for the transmit
path. The Tx port is disabled. The operation of the digital
interface is detailed in the sections that follow.
TRX PORT OPERATION (FULL-DUPLEX MODE)
In full-duplex mode, the TRX port sources the data from the
AD9961/AD9963 I and Q receive channels. The interface
consists of an output data bus (TRXD[11:0]) that carries the
interleaved I and Q data. The data is accompanied by a
qualifying output clock (TRXCLK) and an output signal
(TRXIQ) that identifies the data as from either the I or Q
channel. The maximum guaranteed data rate is 200 MSPS.
The basic timing diagram for the Rx path is shown in Figure 72.
By default, the time-aligned TRXD[11:0] and TRXIQ output
signals are driven on the rising edge of the TRXCLK signal.
The t
An additional configuration bit, RXCLKPH, is available to
invert the TRXCLK. In this case, the TRX data and the TRXIQ
signals are driven out on the falling edge of TRXCLK and t
measured with respect to the falling edge of TRXCLK.
The analog signals are sampled simultaneously, creating a
quadrature pair of data. This creates two possible data pairing
orders on the output bus, I data followed by Q data, or Q data
followed by I data. There are also two possible ways to align the
bus data with the TRXIQ signal, I data aligned with TRXIQ
being high or I data aligned with TRXIQ being low. The IQ
pairing and data to TRXIQ alignment relationships create four
possible timing modes. The AD9961/AD9963 enable any of
these four modes to be sourced from the device. The data
pairing order is controlled by the RX_IFIRST bit. The phase
relationship between the Rx data and the RXIQ signal is
controlled by the RXIQ_HILO bit. The two programming
TRXD[11:0]
OD
TRXCLK
Figure 72. Receive Path Timing Diagram (Bus Rate Clock Mode)
TRXIQ
parameters are specified in Table 23.
t
OD1
I0
Q0
I1
Q1
OD
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is
options produce the four timing diagrams shown in Figure 73.
The output clock on TRXCLK can also be configured as a
double data rate (DDR) clock. In this mode the output clock is
divided by 2 and samples are placed on the TRXD[11:0] bus on
both the rising and falling edges of the TRXCLK. Figure 74
shows the timing.
Table 23. Maximum Output Delay Between TRXCLK/
TRXD[11:0] and TRXIQ Signals from −40°C to +85°C
Parameter
Drive
Strength
t
t
SINGLE ADC MODE
The receive port can be operated with only one of the ADCs
operational. In this mode the TRXCLK signal can operate in
either bus rate clock mode or double data rate clock mode. The
TRXIQ pin indicates which ADC is active. Figure 75 to Figure 78
show the timing options available.
OD1
OD2
TRXD[11 :0]
TRXD[11 :0]
TRXD[11 :0]
TRXD[11 :0]
TRXD[11:0]
TRXIQ
TRXCLK
TRXIQ
Figure 74. Receive Path Timing Diagram (DDR Clock Mode)
Figure 73. Receive Path Data Pairing Options
Min
Q0
Q0
I0
I0
0.55
0.42
Register 0x63 =
0x00
Q0
Q1
I1
I0
I0
Max
0.93
0.67
Q1
Q1
I1
I1
t
OD2
Q0
Q1
Q2
I2
I1
Min
Register 0x63 =
0.36
0.20
Q2
Q2
I 2
I2
0xAA
I1
Max
Q2
Q3
I3
I2
0.57
0.35
RX_IFIRST = 1
RXIQ_HILO = 1
RX_IFIRST = 1
RXIQ_HILO = 0
RX_IFIRST = 0
RXIQ_HILO = 1
RX_IFIRST = 0
RXIQ_HILO = 0
Q1
Units
ns
ns