AD9261 Analog Devices, AD9261 Datasheet - Page 18

• Manufacturer Part Number: AD9261
• Description: 16-Bit, 10 MHz Bandwidth, 30 MSPS to 160 MSPS Continuous Time Sigma-Delta ADC
• Manufacturer: Analog Devices

Specifications of AD9261

• Resolution (bits): 16bit
• # Chan: 1
• Sample Rate: 160MSPS
• Interface: Par
• Analog Input Type: Diff-Uni
• Ain Range: 2 V p-p
• Adc Architecture: Sigma-Delta
• Pkg Type: CSP

AD9261
PLL Autoband Select
The PLL VCO has a wide operating range that is covered by
overlapping frequency bands. For any desired VCO output
frequency, there are multiple valid PLL band select values. The
AD9261 possesses an automatic PLL band select feature on chip
that determines the optimal PLL band setting. This feature can be
enabled by writing to Register 0x0A[6] and is the recommended
configuration with the PLL clocking option. Follow the sequence
shown in Table 9 for enabling the autoband select and configur-
ing the PLL.
When the device is taken out of sleep or standby mode, Register
0x0A[6] must be toggled to reinitiate the autoband detect.
Table 11. Common Modulator Clock Multiplication Factors
CLK±
(MHz)
30.72
39.3216
52.00
61.44
76.80
78.00
78.6432
89.60
92.16
122.88
134.40
153.60
157.2864
Table 12. External PLLMULTx Pins and PLL Multiplication
Factor
PLLMULTx[4:0] Pins
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17 to 30
31
0x0A[5:0]
(PLLMULT)
42
32
25
21
17
17
16
15
14
10
10
8
8
PLL Multiplication Factors (N)
8
9
10
12
14
15
16
17
18
20
21
24
25
28
30
32
34
Direct clocking
42
f
1290.24
1258.29
1300.00
1290.24
1305.60
1326.00
1258.29
1344.00
1290.24
1228.80
1344.00
1228.80
1258.29
VCO
(MHz)
f
(MHz)
645.12
629.15
650.00
645.12
652.80
663.00
629.15
672.00
645.12
614.40
672.00
614.40
629.15
MOD
BW
(MHz)
10.08
9.83
10.16
10.08
10.20
10.36
9.83
10.50
10.08
9.60
10.50
9.60
9.83
Rev. 0 | Page 18 of 28
Jitter Considerations
The aperture jitter requirements for continuous time Σ-Δ conver-
ters may be more forgiving than Nyquist rate converters. The
continuous time Σ-Δ architecture is an oversampled system,
and to accurately represent the analog input signal to the ADC,
a large number of output samples must be averaged together. As a
result, the jitter contribution from each sample is root sum
squared, resulting in a more subtle impact on noise perfor-
mance as compared to Nyquist converters where aperture jitter
has a direct impact on each sampled output.
In the block diagram of the continuous time Σ-Δ modulator
(see Figure 29), the two building blocks most susceptible to
jitter are the quantizer and the DAC. The error introduced
through the sampling process or quantizer is reduced by the
loop gain and shaped in the same way as the quantization noise
and, therefore, its effect can be neglected. On the contrary, the
jitter error associated to the DAC directly adds to the input
signal, thus increasing the in-band noise power and degrading
the modulator performance. The SNR degradation due to jitter
can be represented by the following equation:
where f
The SNR performance of the AD9261 remains constant within
the input bandwidth of the converter, from dc to 10 MHz.
Therefore, the minimal jitter specification is determined at the
highest input frequency. From the calculation, the aperture
jitter of the input clock must be no greater than 1 ps to achieve
optimal SNR performance.
POWER DISSIPATION AND STANDBY MODE
The AD9261 power consumption can be further reduced by
configuring the chip in channel power-down, standby, or sleep
mode. The low power modes turn off internal blocks of the chip
including the reference. As a result, the wake-up time is depen-
dent on the amount of circuitry that is turned off. Fewer internal
circuits that are powered down result in proportionally shorter
wake-up time. The different low power modes are shown in
Table 13. In the standby mode, all clock related activity and the
output channels are disabled. Only the references and CMOS
outputs remain powered up to ensure a short recovery and link
integrity. During sleep mode, all internal circuits are powered
down, putting the device into its lowest power mode, and the
CMOS outputs are disabled.
If the serial port interface is not available, the AD9261 can be
configured in power-down mode by connecting Pin 3 (PDWN)
to AVDD.
SNR = −20 log (2πf
analog
is the analog input frequency and t
analog
t
jitter_rms
) dB
jitter_rms
is the jitter.