AD9261 Analog Devices, AD9261 Datasheet - Page 6

• Manufacturer Part Number: AD9261
• Description: 16-Bit, 10 MHz Bandwidth, 30 MSPS to 160 MSPS Continuous Time Sigma-Delta ADC
• Manufacturer: Analog Devices

Specifications of AD9261

• Resolution (bits): 16bit
• # Chan: 1
• Sample Rate: 160MSPS
• Interface: Par
• Analog Input Type: Diff-Uni
• Ain Range: 2 V p-p
• Adc Architecture: Sigma-Delta
• Pkg Type: CSP

AD9261
SWITCHING SPECIFICATIONS
All power supplies set to 1.8 V, 640 MHz sample rate, 0.5 V internal reference, PLL disabled, 40 MSPS output data rate, AIN = −2.0 dBFS,
unless otherwise noted.
Table 5.
Parameter
CLOCK INPUT (USING CLOCK MULTIPLIER)
CLOCK INPUT (DIRECT CLOCKING)
DATA OUTPUT PARAMETERS
WAKE-UP TIME
OUT-OF-RANGE RECOVERY TIME
SERIAL PORT INTERFACE
1
2
3
4
Timing Diagram
See the AN-83 5 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.
Data skew is measured from DCO 50% transition to data (D0 to D15) 50% transition, with 5 pF load.
Wake-up time is dependent on the value of the decoupling capacitors. Values are shown with 10 μF capacitor on VREF and CFILT.
See Figure 50 and the Serial Port Interface (SPI) section.
Conversion Rate
CLK± Period
CLK± Duty Cycle
Conversion Rate
CLK± Period
CLK± Duty Cycle
Output Data Rate
DCO to Data Skew (t
Sample Latency
Power Down Power
Standby Power
Sleep Power
SCLK Period
SCLK Pulse Width High Time (t
SCLK Pulse Width Low Time (t
SDIO to SCLK Setup Time (t
SDIO to SCLK Hold Time (t
CSB to SCLK Setup Time (t
CSB to SCLK Hold Time (t
1
3
SKEW
4
)
2
SH
D0 TO D15
SS
SDH
)
SDS
)
)
SLOW
)
DCO
SHIGH
)
)
Figure 2. Timing Diagram
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Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
t
SKEW
Min
30
6.25
40
608
1.49
40
20
3
40
16
16
5
2
5
2
Typ
50
640
1.5625
50
960
3
9
15
960
Max
160
33
60
672
1.64
60
168
Unit
MSPS
ns
%
MSPS
ns
%
MSPS
ns
Cycles
μs
μs
μs
Cycles
ns
ns
ns
ns
ns
ns
ns