AD7985 Analog Devices, AD7985 Datasheet - Page 20

• Manufacturer Part Number: AD7985
• Description: 16-Bit, 2.5 MSPS PulSAR 11 mW ADC in QFN
• Manufacturer: Analog Devices

Specifications of AD7985

• Resolution (bits): 16bit
• # Chan: 1
• Sample Rate: 2.5MSPS
• Interface: Ser,SPI
• Analog Input Type: SE-Uni
• Ain Range: (Vref) p-p,Uni (Vref)
• Adc Architecture: SAR
• Pkg Type: CSP

AD7985
CS MODE, 3-WIRE WITH BUSY INDICATOR
This mode is usually used when a single AD7985 is connected
to an SPI-compatible digital host that has an interrupt input. It
is available only in normal conversion mode (TURBO is low).
The connection diagram is shown in Figure 28, and the corre-
sponding timing is given in Figure 29.
With SDI tied to VIO, a rising edge on CNV initiates a con-
version, selects CS mode, and forces SDO to high impedance.
SDO is maintained in high impedance until the completion of
the conversion, irrespective of the state of CNV. Prior to the
minimum conversion time, CNV can be used to select other SPI
devices, such as analog multiplexers, but CNV must be returned
low before the minimum conversion time elapses and then held
low for the maximum possible conversion time to guarantee the
generation of the busy signal indicator.
TURBO = 0
ACQUISITION
SDO
SDI = 1
CNV
SCK
t
CNVH
CONVERSION
t
Figure 29. CS Mode, 3-Wire with Busy Indicator Serial Interface Timing (SDI High)
CONV
Figure 28. CS Mode, 3-Wire with Busy Indicator Connection Diagram (SDI High)
VIO
SDI
AD7985
1
CNV
SCK
t
HSDO
Rev. A | Page 20 of 28
TURBO
D15
2
t
CYC
SDO
ACQUISITION
VIO
D14
t
3
ACQ
47kΩ
t
DSDO
When the conversion is complete, SDO goes from high imped-
ance to low impedance. With a pull-up on the SDO line, this
transition can be used as an interrupt signal to initiate the data
readback controlled by the digital host. The AD7985 then enters
the acquisition phase and powers down. The data bits are then
clocked out, MSB first, by subsequent SCK falling edges. The
data is valid on both SCK edges. Although the rising edge can
be used to capture the data, a digital host using the SCK falling
edge allows a faster reading rate, provided that it has an acceptable
hold time. After the optional 17
to high impedance.
If multiple AD7985 devices are selected at the same time, the
SDO output pin handles this contention without damage or
induced latch-up. Meanwhile, it is recommended that this
contention be kept as short as possible to limit extra power
dissipation.
t
CONVERT
DATA IN
IRQ
CLK
SCKL
DIGITAL HOST
t
SCKH
15
t
SCK
16
D1
17
D0
(I/O QUIET
TIME)
th
t
DIS
SCK falling edge, SDO returns
t
QUIET