AD7985 Analog Devices, AD7985 Datasheet - Page 23

• Manufacturer Part Number: AD7985
• Description: 16-Bit, 2.5 MSPS PulSAR 11 mW ADC in QFN
• Manufacturer: Analog Devices

Specifications of AD7985

• Resolution (bits): 16bit
• # Chan: 1
• Sample Rate: 2.5MSPS
• Interface: Ser,SPI
• Analog Input Type: SE-Uni
• Ain Range: (Vref) p-p,Uni (Vref)
• Adc Architecture: SAR
• Pkg Type: CSP

CHAIN MODE WITHOUT BUSY INDICATOR
This mode can be used to daisy-chain multiple AD7985 devices on
a 3-wire serial interface. It is available only in normal conversion
mode (TURBO is low). This feature is useful for reducing com-
ponent count and wiring connections, for example, in isolated
multiconverter applications or for systems with a limited inter-
facing capacity. Data readback is analogous to clocking a shift
register. A connection diagram example using two AD7985
devices is shown in Figure 34, and the corresponding timing is
given in Figure 35.
When SDI and CNV are low, SDO is driven low. With SCK low,
a rising edge on CNV initiates a conversion, selects chain mode,
and disables the busy indicator. In this mode, CNV is held high
during the conversion phase and the subsequent data readback.
TURBO = 0
SDI
SDO
ACQUISITION
A
A
= 0
t
HSCKCNV
= SDI
CNV
SCK
SDO
B
B
CONVERSION
t
QUIET
t
CONV
t
EN
SDI
t
t
HSDO
DSDO
Figure 35. Chain Mode Without Busy Indicator Serial Interface Timing
AD7985
Figure 34. Chain Mode Without Busy Indicator Connection Diagram
D
D
CNV
SCK
1
A
B
A
15
15
t
SSDISCK
TURBO
D
D
2
A
B
SDO
14
14
D
D
3
A
B
13
13
Rev. A | Page 23 of 28
t
SCKL
SDI
t
HSDISCK
14
AD7985
CNV
SCK
B
t
D
D
15
CYC
A
B
When the conversion is complete, the MSB is output onto SDO,
and the AD7985 enters the acquisition phase and powers down.
The remaining data bits stored in the internal shift register are
clocked by subsequent SCK falling edges. For each ADC, SDI
feeds the input of the internal shift register and is clocked by the
SCK falling edge. Each ADC in the chain outputs its data MSB
first, and 16 × N clocks are required to read back the N ADCs.
The data is valid on both SCK edges. Although the rising edge
can be used to capture the data, a digital host using the SCK
falling edge allows a faster reading rate and consequently more
AD7985 devices in the chain, provided that the digital host has
an acceptable hold time. The maximum conversion rate may be
reduced due to the total readback time.
1
1
ACQUISITION
t
SCK
TURBO
t
SCKH
t
D
D
SDO
16
ACQ
A
B
0
0
D
17
A
15
CONVERT
DATA IN
CLK
DIGITAL HOST
D
18
A
14
30
D
31
A
1
D
32
A
0
AD7985