AD7193 Analog Devices, AD7193 Datasheet - Page 36

• Manufacturer Part Number: AD7193
• Description: 4-Channel, 4.8 kHz, Ultralow Noise, 24-Bit Sigma-Delta ADC with PGA
• Manufacturer: Analog Devices

Specifications of AD7193

• Resolution (bits): 24bit
• # Chan: 4
• Sample Rate: n/a
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni,SE-Uni,Usr-Defined Range/Offset
• Ain Range: ± (Vref/Gain)
• Adc Architecture: Sigma-Delta
• Pkg Type: SOP

AD7193
Continuous Conversion Mode
Continuous conversion is the default power-up mode. The
AD7193 converts continuously, and the RDY bit in the status
register goes low each time a conversion is complete. If CS is
low, the DOUT/ RDY line also goes low when a conversion is
completed. To read a conversion, the user writes to the commu-
nications register, indicating that the next operation is a read of
the data register. When the data-word has been read from the
data register, DOUT/ RDY goes high. The user can read this
register additional times, if required. However, the user must
ensure that the data register is not being accessed at the completion
of the next conversion or else the new conversion word is lost.
DOUT/RDY
SCLK
DIN
CS
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Figure 26. Continuous Conversion
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DATA
When several channels are enabled, the ADC continuously
loops through the enabled channels, performing one conversion
on each channel per loop. The data register is updated as soon
as each conversion is available. The DOUT/ RDY pin pulses low
each time a conversion is available. The user can then read the
conversion while the ADC converts on the next enabled channel.
If the DAT_STA bit in the mode register is set to 1, the contents
of the status register are output along with the conversion each
time that the data read is performed. The status register indicates
the channel to which the conversion corresponds.
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Data Sheet
DATA