AD7193 Analog Devices, AD7193 Datasheet - Page 45

• Manufacturer Part Number: AD7193
• Description: 4-Channel, 4.8 kHz, Ultralow Noise, 24-Bit Sigma-Delta ADC with PGA
• Manufacturer: Analog Devices

Specifications of AD7193

• Resolution (bits): 24bit
• # Chan: 4
• Sample Rate: n/a
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni,SE-Uni,Usr-Defined Range/Offset
• Ain Range: ± (Vref/Gain)
• Adc Architecture: Sigma-Delta
• Pkg Type: SOP

Data Sheet
Simultaneous 50 Hz and 60 Hz rejection is obtained when
FS[9:0] is set to 480 (master clock = 4.92 MHz), as shown in
Figure 42. The output data rate is 10 Hz when zero latency is
disabled and 3.3 Hz when zero latency is enabled. The sinc
filter has rejection of 100 dB minimum at 50 Hz ± 1 Hz and
60 Hz ± 1 Hz.
Simultaneous 50 Hz/60 Hz rejection is also achieved using the
REJ60 bit in the mode register. When FS[9:0] is programmed to
96 and the REJ60 bit is set to 1, notches are placed at both 50 Hz
and 60 Hz for a stable 4.92 MHz master clock. Figure 43 shows
the frequency response of the sinc
Assuming a stable clock, the rejection at 50 Hz/60 Hz (±1 Hz) is
in excess of 67 dB minimum.
–100
–120
–110
–100
–120
–110
–10
–20
–30
–40
–50
–60
–70
–80
–90
–10
–20
–30
–40
–50
–60
–70
–80
–90
0
0
0
0
Figure 43. Sinc
Figure 42. Sinc
25
30
3
Filter Response (FS[9:0] = 96, REJ60 = 1)
50
3
Filter Response (FS[9:0] = 480)
FREQUENCY (Hz)
FREQUENCY (Hz)
60
3
75
filter with this configuration.
90
100
120
125
150
150
3
Rev. C | Page 45 of 56
CHOP ENABLED (SINC
With chop enabled, the ADC offset and offset drift are minimized.
The analog input pins are continuously swapped. With the analog
input pins connected in one direction, the settling time of the
sinc filter is allowed and a conversion is recorded. The analog
input pins are then inverted, and another settled conversion is
obtained. Subsequent conversions are averaged to minimize the
offset. This continuous swapping of the analog input pins and
the averaging of subsequent conversions means that the offset
drift is also minimized. With chop enabled, the resolution
increases by 0.5 bits.
Output Data Rate and Settling Time (Sinc
For the sinc
where:
f
f
FS[9:0] is the decimal equivalent of Bit FS9 to Bit FS0 in the
mode register.
The value of FS[9:0] can be varied from 1 to 1023. This results
in an output data rate of 1.17 Hz to 1200 Hz. The settling time is
equal to
Table 32 gives some examples of FS[9:0] values and the
corresponding output data rates and settling times.
Table 32. Examples of Output Data Rates and the
Corresponding Settling Time
FS[9:0]
96
80
ADC
CLK
is the master clock (4.92 MHz nominal).
is the output data rate.
f
t
ADC
SETTLE
= f
CHOP
= 2/f
4
CLK
filter, the output data rate is equal to
/(4 × 1024 × FS[9:0])
ADC
Output Data Rate (Hz)
12.5
15
MODULATOR
Figure 44. Chop Enabled
4
FILTER)
ADC
SINC
3
/SINC
4
POST FILTER
4
Settling Time (ms)
160
133
Chop Enabled)
AD7193