AD7193 Analog Devices, AD7193 Datasheet - Page 50

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AD7193

Manufacturer Part Number
AD7193
Description
4-Channel, 4.8 kHz, Ultralow Noise, 24-Bit Sigma-Delta ADC with PGA
Manufacturer
Analog Devices
Datasheet

Specifications of AD7193

Resolution (bits)
24bit
# Chan
4
Sample Rate
n/a
Interface
Ser,SPI
Analog Input Type
Diff-Uni,SE-Uni,Usr-Defined Range/Offset
Ain Range
± (Vref/Gain)
Adc Architecture
Sigma-Delta
Pkg Type
SOP

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AD7193
FAST SETTLING MODE (SINC
In fast settling mode, the settling time is close to the inverse of
the first filter notch. Therefore, the user can achieve 50 Hz and/or
60 Hz rejection at an output data rate close to 1/50 Hz or 1/60 Hz.
The settling time is equal to 1/output data rate. Therefore, the
conversion time is constant when converting on a single channel
or when converting on several channels. There is no added
latency when switching channels.
The fast settling mode is enabled using Bit AVG1 and Bit AVG0
in the mode register. A postfilter is included after the sinc
The postfilter averages by 2, 8, or 16, depending on the settings
of the AVG1 and AVG0 bits.
Output Data Rate and Settling Time, Sinc
With chop disabled, the output data rate is
f
f
Avg is the average.
FS[9:0] is the decimal equivalent of Bit FS9 to Bit FS0 in the
mode register.
If AVG1 = AVG0 = 0, the fast settling mode is not enabled.
In this case, the preceding equation is not relevant.
The settling time is equal to
Table 35 lists some sample FS words and the corresponding
output data rates and settling times.
Table 35. Examples of Output Data Rates and the
Corresponding Settling Time (Fast Settling Mode, Sinc
FS[9:0]
96
30
6
5
If the analog input channel is changed, there is no additional
delay in generating valid conversions and the device functions
as a zero latency ADC.
ADC
CLK
CONVERSIONS
is master clock (4.92 MHz nominal).
is the output data rate.
f
t
ADC
SETTLE
CHANNEL
= f
CHOP
Average
16
16
16
16
= 1/f
CLK
/((3 + Avg – 1) × 1024 × FS[9:0])
Figure 61. Fast Settling Mode, Sinc
CH A
ADC
CHANNEL A
MODULATOR
Figure 62. Fast Settling, Sinc
CH A CH A
Output Data Rate (Hz)
2.78
8.9
44.44
53.3
ADC
SINC
CH B
3
/SINC
3
1/
FILTER)
CH B
f
CHANNEL B
ADC
4
3
Filter
CH B
POST FILTER
3
Filter
Settling Time (ms)
360
112.5
22.5
18.75
3
CH B
Filter
CH B
4
filter.
CH B
3
)
Rev. C | Page 50 of 56
When the device is converting on a single channel and a step
change occurs on the analog input, the ADC does not detect
the change and continues to output conversions. When the step
change is synchronized with the conversion, only fully settled
results are output from the ADC. However, if the step change is
asynchronous to the conversion process, one intermediate result
is not completely settled (see Figure 63).
50 Hz/60 Hz Rejection, Sinc
Figure 64 shows the frequency response when FS[9:0] is set to 6
and the postfilter averages by 16. This gives an output data rate
of 44.44 Hz when the master clock is 4.92 MHz. The sinc filter
places the first notch at
The postfiltering places notches at f
of averaging) and multiples of this frequency. Therefore, when
FS[9:0] is set to 6 and the postfilter averaging is 16, a notch is
placed at 800 Hz due to the sinc filter and notches are placed at
50 Hz and multiples of 50 Hz due to the postfilter.
The notch at 50 Hz is a first-order notch. Therefore, the notch is
not wide. This means that the rejection at 50 Hz exactly is good,
assuming a stable 4.92 MHz master clock. However, in a band of
50 Hz ± 1 Hz, the rejection degrades significantly. The rejection at
50 Hz ± 0.5 Hz is 40 dB minimum, assuming a stable clock; there-
fore, a good master clock source is recommended when using fast
settling mode.
ANALOG
OUTPUT
INPUT
f
ADC
–100
–120
NOTCH
–110
–10
–20
–30
–40
–50
–60
–70
–80
–90
0
Figure 64. Filter Response for Average + Decimate Filter
0
Figure 63. Step Change on Analog Input, Sinc
= f
CLK
(Sinc
/(1024 × FS[9:0])
30
3
Filter, FS[9:0] = 6, Average by 16)
FREQUENCY (Hz)
60
3
Filter
NOTCH
90
/Avg (Avg is the amount
120
Data Sheet
3
Filter
VALID
1/
f
ADC
150

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