AD7781 Analog Devices, AD7781 Datasheet
AD7781
Specifications of AD7781
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AD7781 Summary of contents
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... The settling time is 300 ms at this update rate. Simultaneous 50 Hz rejection occurs at both the 10 Hz and 16.7 Hz update rates. The AD7781 operates with a power supply from 2 5. available in a narrow body, 14-lead SOIC package and in a 16-lead TSSOP package. ...
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... Data Output Coding .................................................................. 12 Reference ..................................................................................... 12 Bridge Power-Down Switch ...................................................... 12 Digital Interface .......................................................................... 13 Applications Information .............................................................. 14 Weigh Scales ................................................................................ 14 AD7781 Performance in a Weigh Scale System ......................... 14 EMI Recommendations ............................................................. 14 Grounding and Layout .............................................................. 15 Outline Dimensions ....................................................................... 16 Ordering Guide .......................................................................... 16 Rev Page ...
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... 400 ±0.15 110 9 30 Rev Page AD7781 unless otherwise noted. MIN MAX Unit Test Conditions/Comments Hz FILTER = 1, settling time = 3/f Hz FILTER = 0, settling time = 2/f Bits See Table 7 and Table 8 See Table 7 and Table 8 ppm FSR μV Gain = 128 with FILTER = 1 μ ...
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... AD7781 Parameter INTERNAL CLOCK Frequency 64 − 3% Duty Cycle LOGIC INPUTS 2 SCLK, FILTER, GAIN, PDRST Input Low Voltage, V INL Input High Voltage, V 1.8 INH 2.4 SCLK (Schmitt-Triggered Input) 2 Hysteresis Input Currents Input Capacitance LOGIC OUTPUT (DOUT/RDY) 2 Output High Voltage Output Low Voltage, V ...
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... GAIN OR FILTER t 4 DOUT/RDY Rev Page unless otherwise noted (10 and timed from a voltage level of 1 limits Figure 4. Resetting the AD7781 (INPUT (OUTPUT) Figure 5. Changing Gain or Filter Option AD7781 ...
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... AD7781 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 4. Parameter AV to GND GND DD Analog Input Voltage to GND Reference Input Voltage to GND Digital Input Voltage to GND Digital Output Voltage to GND AIN/Digital Input Current Operating Temperature Range Storage Temperature Range Maximum Junction Temperature ...
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... Serial Clock Input. This serial clock input is for data transfers from the ADC. The SCLK pin has a Schmitt- triggered input. The serial clock can be active only when transferring data from the AD7781. The data from the AD7781 can be read as a continuous 32-bit word. Alternatively, SCLK can be noncontinuous during the data transfer, with the information being transmitted from the ADC in smaller data batches ...
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... AD7781 TYPICAL PERFORMANCE CHARACTERISTICS 524,294 524,293 524,292 524,291 524,290 524,289 524,288 524,287 524,286 0 200 400 600 SAMPLE Figure 8. C Grade Noise ( Update Rate = 16.7 Hz, Gain = 128) REF DD 500 400 300 200 100 0 524,286 524,288 524,290 CODE Figure 9. C Grade Noise Distribution Histogram ...
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... Rev Page –6 –4 – (V) IN Figure 17. Integral Nonlinearity ( Gain = 1) REF DD –40 – TEMPERATURE (°C) Figure 18. Offset vs. Temperature (Gain = 128) –40 – TEMPERATURE (°C) Figure 19. Gain Error vs. Temperature (Gain = 128) AD7781 4 6 100 120 100 120 ...
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... OUTPUT NOISE AND RESOLUTION Table 7 and Table 8 show the rms noise of the AD7781 for the two output data rates and gain settings when using and reference. These numbers are typical and are generated with a differential input voltage The peak-to-peak (p-p) resolution is also listed. The p-p resolution represents the resolution for which there is no code flicker ...
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... Figure 21. Filter Profile with Update Rate = 10 Hz (FILTER = 1) GAIN The AD7781 has two gain options: gain = 1 and gain = 128. When the GAIN pin is low, the gain is set to 128; when the GAIN pin is high, the gain is set to 1. The acceptable analog input range is ± ...
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... PDRST must be held low for 100 ns minimum to initiate the reset function (see Figure 4 ). When PDRST is taken high, the AD7781 is taken out of power- down mode. When the on-chip clock has powered up (1 ms, typically), the modulator begins sampling the analog input. The low-side power switch is closed, and the DOUT/ RDY pin becomes active ...
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... ID bits. ID1 ID0 0 0 GAIN Gain bit. 1: gain = 1. 0: gain = 128. PAT1, PAT0 Status pattern bits. When the user reads data from the AD7781, a pattern check can be performed. PAT1 PAT0 When a conversion is complete, the serial interface is reset, and the new conversion is placed in the data register ...
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... AD7781 using a microprocessor increases the p-p resolution. For example, an average the microprocessor increases the accuracy by 2 bits. The noise-free counts value is equal to Noise-Free Counts = (2 where: Effective Bits = 18.2 bits (AD7781 bits (due to postprocessing in the microprocessor the full-scale signal from the load cell (10 mV ...
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... The ground plane of the AD7781 should be allowed to run under the AD7781 to prevent noise coupling. The power supply lines to the AD7781 should use as wide a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals such as clocks should ...
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... AD7781BRUZ −40°C to +105°C 1 AD7781BRUZ-REEL −40°C to +105°C AD7781CRZ 1 −40°C to +105°C 1 AD7781CRZ-REEL −40°C to +105°C 1 AD7781CRUZ −40°C to +105°C 1 AD7781CRUZ-REEL −40°C to +105° RoHS Compliant Part. ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners ...