AD7452 Analog Devices, AD7452 Datasheet

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AD7452

Manufacturer Part Number
AD7452
Description
Differential Input, 555 kSPS, 12-Bit A/D Converter in 8-Lead SOT-23
Manufacturer
Analog Devices
Datasheet

Specifications of AD7452

Resolution (bits)
12bit
# Chan
1
Sample Rate
555kSPS
Interface
Ser,SPI
Analog Input Type
Diff-Uni
Ain Range
(2Vref) p-p
Adc Architecture
SAR
Pkg Type
SOT

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FEATURES
Specified for V
Low power at max throughput rate:
Fully differential analog input
Wide input bandwidth:
Flexible power/serial clock speed management
No pipeline delays
High speed serial interface:
Power-down mode: 1 µA max
8-lead SOT-23 package
APPLICATIONS
Transducer interface
Battery-powered systems
Data acquisition systems
Portable instrumentation
Motor control
GENERAL DESCRIPTION
The AD7452
approximation (SAR) analog-to-digital converter that features a
fully differential analog input. This part operates from a single
3 V or 5 V power supply and features throughput rates up to
555 kSPS.
The part contains a low noise, wide bandwidth, differential
track-and-hold amplifier (T/H) that can handle input
frequencies up to 3.5 MHz. The reference voltage is applied
externally to the V
3.5 V depending on the power supply and what suits the
application. The value of the reference voltage determines the
common-mode voltage range of the part. With this truly
differential input structure and variable reference input, the
user can select a variety of input ranges and bias points.
The conversion process and data acquisition are controlled
using CS and the serial clock, allowing the device to interface
with microprocessors or DSPs. The input signals are sampled on
the falling edge of CS , and the conversion is also initiated at this
point.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
3.3 mW max at 555 kSPS with 3 V supplies
7.25 mW max at 555 kSPS with 5 V supplies
70 dB SINAD at 100 kHz input frequency
SPI®/QSPI™/MICROWIRE™/DSP compatible
1
is a 12-bit, high speed, low power, successive
DD
of 3 V and 5 V
REF
pin and can be varied from 100 mV to
12-Bit ADC in an 8-Lead SOT-23
The SAR architecture of this part ensures that there are no
pipeline delays.
The AD7452 uses advanced design techniques to achieve very
low power dissipation.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
6.
7.
8.
1
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
Protected by U.S. Patent Number 6,681,332.
V
V
V
REF
Operation with Either 3 V or 5 V Power Supplies.
High Throughput with Low Power Consumption. With a
3 V supply, the AD7452 offers 3.3 mW max power
consumption for 555 kSPS throughput.
Fully Differential Analog Input.
Flexible Power/Serial Clock Speed Management. The
conversion rate is determined by the serial clock, allowing
the power to be reduced as the conversion time is reduced
through the serial clock speed increase. This part also
features a shutdown mode to maximize power efficiency at
lower throughput rates.
Variable Voltage Reference Input.
No Pipeline Delay.
Accurate Control of the Sampling Instant via a CS Input
and Once-Off Conversion Control.
ENOB > 8 Bits Typically with 100 mV Reference.
IN+
IN–
Differential Input, 555 kSPS
FUNCTIONAL BLOCK DIAGRAM
GND
V
AD7452
DD
T/H
© 2004 Analog Devices, Inc. All rights reserved.
Figure 1.
APPROXIMATION
CONTROL LOGIC
SUCCESSIVE
12-BIT
ADC
www.analog.com
AD7452
SCLK
SDATA
CS

AD7452 Summary of contents

Page 1

... PRODUCT HIGHLIGHTS 1. Operation with Either Power Supplies. 2. High Throughput with Low Power Consumption. With supply, the AD7452 offers 3.3 mW max power consumption for 555 kSPS throughput. 3. Fully Differential Analog Input. 4. Flexible Power/Serial Clock Speed Management. The ...

Page 2

... Changes to Timing Specifications .............................................. 5 Changes to Timing Example ..................................................... 19 9/03—Revision 0: Initial Version Reference ..................................................................................... 18 Single-Ended Operation............................................................ 18 Serial Interface ............................................................................ 19 Modes of Operation ....................................................................... 20 Normal Mode.............................................................................. 20 Power-Down Mode .................................................................... 20 Power-Up Time .......................................................................... 21 Power vs. Throughput Rate....................................................... 22 Microprocessor and DSP Interfacing ...................................... 22 Application Hints ....................................................................... 24 Evaluating the AD7452’s Performance .................................... 24 Outline Dimensions ....................................................................... 25 Ordering Guide .......................................................................... 25 Rev Page ...

Page 3

... Typically 200 µA DD SOURCE 200 µA DD SOURCE I = 200 µA SINK Rev Page AD7452 = 10 MHz 555 kSPS 2.5 V; SCLK S REF 2 B Version Unit 70 dB min –76 dB max –74 dB max –76 dB max –74 dB max – ...

Page 4

... Because the input spans of V and V are both V IN+ IN– 6 The AD7452 is functional with a reference input from 100 mV; for V 7 The AD7452 is functional with a reference input from 100 mV; for V 8 Guaranteed by characterization. 9 See Power vs. Throughput Rate section. 10 Measured with a midscale dc input. ...

Page 5

... V voltage MHz 555 kSPS 2.5 V; SCLK S REF QUIET DB1 DB0 THREE-STATE = 0 2.0 V for Figure 3. The measured number is then extrapolated , quoted in the Timing Specifications is the true bus relinquish 8 AD7452 = 3 V. ...

Page 6

... AD7452 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 3. Parameter V to GND GND IN GND IN– Digital Input Voltage to GND Digital Output Voltage to GND V to GND REF Input Current to Any Pin Except Supplies Operating Temperature Range Commercial (B Version) Storage Temperature Range Junction Temperature θ ...

Page 7

... Mnemonic Function V Reference Input for the AD7452. An external reference must be applied to this input. For power supply, the reference is REF 2.5 V (± 1%) for specified performance. For power supply, the reference (± 1%) for specified performance. This pin should be decoupled to GND with a capacitor of at least 0.1 µF. See the Reference section for more details. ...

Page 8

... The AD7452 is tested using the CCIF standard where two input frequencies near the top end of the input bandwidth are used. In this case, the second-order terms are usually distanced in frequency from the original sine waves while the third-order terms are usually at a frequency close to the input frequencies ...

Page 9

... REF ADC V DD varies from 1 kHz to 1 MHz the power at frequency f in the ADC output; Pfs is the + 1 LSB), after REF power at frequency f Rev Page supply of frequency f . The frequency of this input S PSRR(dB) = 10log(Pf/ the ADC output. S AD7452 ...

Page 10

... AD7452 AD7452–TYPICAL PERFORMANCE CHARACTERISTICS T = 25° 555 kSPS MHz, unless otherwise noted SCLK 5.25V 3. FREQUENCY (kHz) Figure 5. SINAD vs. Analog Input Frequency for Various Supply Voltages 0 –10 –20 –30 –40 –50 – –70 DD – ...

Page 11

... Figure 15. Change in Zero-Code Error vs. Reference Voltage V 12.0 11.5 V 11.0 10.5 10.0 9.5 9.0 8.5 8.0 7.5 7.0 3.0 3 Figure 16. Change in ENOB vs. Reference Voltage V Rev Page POSITIVE INL NEGATIVE INL 0.5 1.0 1.5 2.0 2.2 V (V) REF Figure 14. Change in INL vs. V for REF 0.5 1.0 1.5 2.0 2.5 3.0 V (V) REF 0.5 1.0 1.5 2.0 2.5 3.0 V (V) REF = 5 V and AD7452 2.5 3 and 3 V 3.5 ...

Page 12

... AD7452 10,000 IN+ IN– 9,000 10,000 CONVERSIONS 10,000 f = 555kSPS CODES S 8,000 7,000 6,000 5,000 4,000 3,000 2,000 1,000 0 2044 2045 2046 2047 CODE Figure 17. Histogram of 10,000 Conversions Input with V 2048 2049 = Rev Page ...

Page 13

... V IN– ADC TRANSFER FUNCTION The output coding for the AD7452 is twos complement. The designed code transitions occur at successive LSB values (i.e., 1 LSB, 2 LSBs, and so on). The LSB size is 2 × V The ideal transfer characteristic of the AD7452 is shown in Figure 20. 011...111 011 ...

Page 14

... AD7452 TYPICAL CONNECTION DIAGRAM Figure 21 shows a typical connection diagram for the AD7452 for both 5 V and 3 V supplies. In this setup, the GND pin is connected to the analog ground plane of the system. The V pin is connected to either a 2 decoupled reference source, depending on the power supply, to set up the analog input range ...

Page 15

... REF Analog Input Structure Figure 26 shows the equivalent circuit of the analog input structure of the AD7452. The four diodes provide ESD protection for the analog inputs. Care must be taken to ensure that the analog input signals never exceed the supply rails by more than 300 mV. This causes these diodes to become forward-biased and start conducting into the substrate ...

Page 16

... Differential Amplifier An ideal method of applying differential drive to the AD7452 is to use a differential amplifier such as the AD8138. This part can be used as a single-ended-to-differential amplifier differential-to-differential amplifier. In both cases, the analog input needs to be bipolar ...

Page 17

... Op Amp Pair An op amp pair can be used to directly couple a differential signal to the AD7452. The circuit configurations shown in Figure 30 and Figure 31 show how a dual op amp can be used to convert a single-ended signal into a differential signal for both a bipolar and unipolar input signal, respectively. The voltage applied to Point A sets up the common-mode voltage ...

Page 18

... AD780 ADR421 ADR420 SINGLE-ENDED OPERATION When supplied with power supply, the AD7452 can han- dle a single-ended input. The design of this part is optimized for differential operation, so with a single-ended input, perfor- mance degrades. Linearity degrades by 0.2 LSB typically, the full-scale errors degrade by 1 LSB typically, and ac performance ...

Page 19

... AD7452 consists of four leading zeros followed by 12 bits of conversion data provided MSB first. The output coding is twos complement. Sixteen serial clock cycles are required to perform a conversion and access data from the AD7452. CS going low provides the first leading zero to be read in by the microcontroller or DSP. CS 10ns ...

Page 20

... AD7452 MODES OF OPERATION The mode of operation of the AD7452 is selected by controlling the logic state of the CS signal during a conversion. There are two possible modes of operation, normal and power-down. The point at which CS is pulled high after the conversion has been initiated determines whether or not the AD7452 enters the power-down mode ...

Page 21

... CS . When running at the maximum throughput rate of 555 kSPS, the AD7452 powers up and acquires a signal within ±0.5 LSB in one dummy cycle. When powering up from the power-down mode with a dummy cycle Figure 38, the track-and-hold, ...

Page 22

... For the same scenario the power dissipation during DD normal operation is 3.3 mW max. The AD7452 can now be said to dissipate 3.3 mW for 2.66 µs during each conversion cycle. The average power dissipated during each cycle with a throughput rate of 100 kSPS is therefore (2.66/10) × 3 0.88 mW This is how the power numbers in Figure 39 are calculated ...

Page 23

... FSL1 = 0 and FSL0 = 0 in CRB). Set the word length setting Bits WL1 = 1 and WL0 = 0 in CRA. To implement power-down mode on the AD7452, the word length can be changed to eight bits by setting Bits WL1 = 0 and WL0 = 0 in CRA. It should be noted that for signal processing applications imperative that the frame synchronization signal from the DSP56xxx provides equidistant sampling ...

Page 24

... The analog ground plane should be allowed to run under the AD7452 to avoid noise coupling. The power supply lines to the AD7452 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. ...

Page 25

... Evaluation board controller. This board is a complete unit allowing control and communicate with all Analog Devices’ evaluation boards ending in the CB designator. For a complete evaluation kit, you need to order the ADC evaluation board, i.e., EVAL-AD7452CB, the EVAL-CONTROL BRD2, and transformer. See the see the AD7452 application note that accompanies the evaluation kit for more information ...

Page 26

... AD7452 NOTES Rev Page ...

Page 27

... NOTES Rev Page AD7452 ...

Page 28

... AD7452 NOTES © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C03154–0–2/04(B) Rev Page ...

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