AD7452 Analog Devices, AD7452 Datasheet - Page 20

• Manufacturer Part Number: AD7452
• Description: Differential Input, 555 kSPS, 12-Bit A/D Converter in 8-Lead SOT-23
• Manufacturer: Analog Devices

Specifications of AD7452

• Resolution (bits): 12bit
• # Chan: 1
• Sample Rate: 555kSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni
• Ain Range: (2Vref) p-p
• Adc Architecture: SAR
• Pkg Type: SOT

AD7452
MODES OF OPERATION
The mode of operation of the AD7452 is selected by controlling
the logic state of the CS signal during a conversion. There are
two possible modes of operation, normal and power-down. The
point at which CS is pulled high after the conversion has been
initiated determines whether or not the AD7452 enters the
power-down mode. Similarly, if already in power-down, CS
controls whether the device returns to normal operation or
remains in power-down. These modes of operation are designed
to provide flexible power management options. These options
can be chosen to optimize the power dissipation/throughput
rate ratio for differing application requirements.
NORMAL MODE
This mode is intended for fastest throughput rate performance.
The user does not have to worry about any power-up times with
the AD7452 remaining fully powered up all the time. Figure 36
shows the general diagram of the AD7452’s operation in this
mode. The conversion is initiated on the falling edge of CS , as
described in the Serial Interface section. To ensure that the part
remains fully powered up, CS must remain low until at least 10
SCLK falling edges have elapsed after the falling edge of CS .
If CS is brought high any time after the 10
but before the 16
up but the conversion is terminated and SDATA goes back into
three-state. Sixteen serial clock cycles are required to complete
the conversion and access the complete conversion result. CS
may idle high until the next conversion or may idle low until
sometime prior to the next conversion. Once a data transfer is
complete, i.e., when SDATA has returned to three-state, another
conversion can be initiated after the quiet time, t
elapsed by again bringing CS low.
SDATA
SCLK
CS
th
Figure 36. Normal Mode Operation
4 LEADING ZEROS + CONVERSION RESULT
1
SCLK falling edge, the part remains powered
10
th
SCLK falling edge,
16
QUIET
, has
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POWER-DOWN MODE
This mode is intended for use in applications where slower
throughput rates are required; either the ADC is powered down
between each conversion, or a series of conversions may be
performed at a high throughput rate and the ADC is then
powered down for a relatively long duration between these
bursts of several conversions. When the AD7452 is in power-
down mode, all analog circuitry is powered down. To enter
power-down mode, the conversion process must be interrupted
by bringing CS high anywhere after the second falling edge of
SCLK, and before the 10
Figure 37.
Once CS has been brought high in this window of SCLKs, the
part enters power-down, the conversion that was initiated by
the falling edge of CS is terminated, and SDATA goes back into
three-state. The time from the rising edge of CS to SDATA
three-state enabled is never greater than t
Specifications). If CS is brought high before the second SCLK
falling edge, the part remains in normal mode and does not
power down. This avoids accidental power-down due to glitches
on the CS line.
In order to exit this mode of operation and power up the
AD7452 again, a dummy conversion is performed. On the
falling edge of CS , the device begins to power up and continues
to power up as long as CS is held low until after the falling edge
of the 10
elapsed and, as shown in Figure 38, valid data results from the
next conversion.
If CS is brought high before the 10
AD7452 again goes back into power-down. This avoids acci-
dental power-up due to glitches on the CS line or an inadvertent
burst of eight SCLK cycles while CS is low. So although the
device may begin to power up on the falling edge of CS , it again
powers down on the rising edge of CS as long as it occurs before
the 10
SDATA
SCLK
th
CS
SCLK falling edge.
th
SCLK. The device is fully powered up after 1 µs has
Figure 37. Entering Power-Down Mode
1
2
th
falling edge of SCLK, as shown in
th
10
falling edge of SCLK, the
THREE-STATE
8
(refer to the Timing