AD7452 Analog Devices, AD7452 Datasheet - Page 23

• Manufacturer Part Number: AD7452
• Description: Differential Input, 555 kSPS, 12-Bit A/D Converter in 8-Lead SOT-23
• Manufacturer: Analog Devices

Specifications of AD7452

• Resolution (bits): 12bit
• # Chan: 1
• Sample Rate: 555kSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni
• Ain Range: (2Vref) p-p
• Adc Architecture: SAR
• Pkg Type: SOT

The timer registers, for example, are loaded with a value that
provides an interrupt at the required sample interval. When an
interrupt is received, a value is transmitted with TFS/DT (ADC
control word). The TFS is used to control the RFS and therefore
the reading of data. The frequency of the serial clock is set in
the SCLKDIV register. When the instruction to transmit with
TFS is given (i.e., AX0 = TX0), the state of the SCLK is checked.
The DSP waits until the SCLK has gone high, low, and high
again before the transmission starts. If the timer and SCLK
values are chosen such that the instruction to transmit occurs
on or near the rising edge of SCLK, the data may be transmitted
or it may wait until the next clock edge.
For example, the ADSP-2111 has a master clock frequency of
16 MHz. If the SCLKDIV register is loaded with the value 3, an
SCLK of 2 MHz is obtained and eight master clock periods
elapse for every SCLK period. If the timer registers are loaded
with the value 803, 100.5 SCLKs occur between interrupts and
subsequently between transmit instructions. This situation
results in nonequidistant sampling because the transmit
instruction is occurring on an SCLK edge. If the number of
SCLKs between interrupts is a whole integer figure of N,
equidistant sampling is implemented by the DSP.
AD7452 to TMS320C5x/C54x
The serial interface on the TMS320C5x/C54x uses a continuous
serial clock and frame synchronization signals to synchronize
the data transfer operations with peripheral devices like the
AD7452. The CS input allows easy interfacing between the
TMS320C5x/C54x and the AD7452 without any glue logic
required. The serial port of the TMS320C5x/C54x is set up to
operate in burst mode with internal CLKx (Tx serial clock) and
FSx (Tx frame sync). The serial port control register (SPC) must
have the following setup: FO = 0, FSM = 1, MCM = 1, and TxM
= 1. The format bit, FO, may be set to 1 to set the word length to
eight bits in order to implement the power-down mode on the
AD7452. The connection diagram is shown in Figure 41. It
should be noted that for signal processing applications, it is
imperative that the frame synchronization signal from the
TMS320C5x/C54x provides equidistant sampling.
*ADDITIONAL PINS REMOVED FOR CLARITY
AD7452*
SDATA
SCLK
CS
Figure 40. Interfacing to the ADSP-21xx
SCLK
DR
RFS
TFS
ADSP-21xx*
Rev. B | Page 23 of 28
AD7452 to DSP56xxx
The connection diagram in Figure 42 shows how the AD7452
can be connected to the SSI (synchronous serial interface) of
the DSP56xxx family of DSPs from Motorola. The SSI is
operated in synchronous mode (SYN bit in CRB = 1) with
internally generated 1-word frame sync for both Tx and Rx
(Bits FSL1 = 0 and FSL0 = 0 in CRB). Set the word length to 16
by setting Bits WL1 = 1 and WL0 = 0 in CRA. To implement
power-down mode on the AD7452, the word length can be
changed to eight bits by setting Bits WL1 = 0 and WL0 = 0 in
CRA. It should be noted that for signal processing applications,
it is imperative that the frame synchronization signal from the
DSP56xxx provides equidistant sampling.
*ADDITIONAL PINS REMOVED FOR CLARITY
*ADDITIONAL PINS REMOVED FOR CLARITY
AD7452*
AD7452*
SDATA
SDATA
SCLK
SCLK
Figure 41. Interfacing to the TMS320C5x/C54x
CS
CS
Figure 42. Interfacing to the DSP56xxx
SCLK
SRD
SR2
CLKx
CLKR
DR
FSx
FSR
TMS320C5x/
DSP56xxx*
C54x*
AD7452