AD9861 Analog Devices, AD9861 Datasheet - Page 27

• Manufacturer Part Number: AD9861
• Manufacturer: Analog Devices

Specifications of AD9861

• Resolution (bits): 10bit
• # Chan: 2
• Sample Rate: 80MSPS
• Interface: Par
• Analog Input Type: Diff-Uni
• Ain Range: 2 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

AUXILIARY CONVERTERS
The AD9861 contains auxiliary analog-to-digital converters
(AuxADCs) and auxiliary digital-to-analog converters
(AuxDACs). These auxiliary converters can be used to measure
or force system-wide control signals.
By default, the auxiliary converters are disabled and powered
down. Enabling and controlling the auxiliary converters is
achieved through the serial programmable registers.
Pins 29, 30, and 46 are configurable either as AuxDAC outputs
or as AuxADC inputs. The respective AuxADC inputs are
connected to the external pin when a conversion is initiated and
are disconnected when the conversion is complete. The
AuxDAC outputs are enabled by writing to the respective
power-up registers in Register 0x29.
•
•
•
Auxiliary DACs
The AD9861 integrates three 8-bit voltage output auxiliary
digital-to-analog converters (AuxDACs), which can be used for
supplying various control voltages throughout the system such
as a VCXO voltage control or external VGA gain control. The
AuxDACs have a programmable full-scale output voltage, V
and can be synchronized to update with a single register write
or a rising edge on the TxPwrDwn pin.
By default, the AuxDAC outputs are powered down and require
a serial write to the power-up registers [Register 0x29, Bits 2–0]
to enable them.
The full-scale output of each AuxDAC is independently
programmable to the full scales of 2.5 V, 2.7 V, 3.0 V, or 3.3 V by
using Serial Register 0x17. The AuxDAC outputs have an I-to-V
driver that produces a voltage output that settles to ±1 LSB
within 0.5 µs. The output driver is capable of sinking or sourcing
up to 6 mA. Using the AuxDAC requires the SPI to be operational.
The AuxDACs are based on a resistor divider network. The
AuxDACs output level is proportional to the straight binary
input codes from the appropriate SPI registers, Registers 0x24
to 0x26. By default, the AuxDAC output is updated immediately
following the register write, but the update can occur
synchronously to a single register write or to the TxPwrDwn
rising edge.
In slave mode, the AuxDAC update occurs when a logic high is
written to the appropriate update registers [Register 0x28, Bits 2–0,
Pin 29 can be connected to AuxDAC_A and/or
AuxADC_A Channel 2.
Pin 30 can be connected to AuxDAC_B and/or
AuxADC_A Channel 1.
Pin 46 can be connected to AuxDAC_C and/or
AuxADC_B.
OUTFS
Rev. 0 | Page 27 of 52
,
Update C, B, and A]. Slave mode is enabled by writing a high to
the slave mode register bit [Register 0x28, Bit 7, Slave Enable].
Another synchronization mode allows any combination of
AuxDACs to be updated along with an externally applied rising
edge to the TxPwrDwn pin.
Typical settling time for the AuxDAC output is less than 0.5 µs,
but is dependent on the load.
Auxiliary ADCs
Two auxiliary 10-bit SAR analog-to-digital converters
(AuxADCs) are available for monitoring various external
signals throughout the system, such as a receive signal strength
indicator (RSSI) function or temperature indicator. The
AuxADCs have many SPI programmable options. Register
settings can be used to configure various full-scale reference
options, change the sampling rate, and average multiple sample
readings. By default, the AuxADC start conversion and output
value is accessed through the register map. Additionally an
auxiliary serial port can be enabled and used to initiate a
conversion and read back the AuxADC data. The auxiliary
serial port interface is available so that the normal SPI can be
used to program other options while the AuxADC is accessed.
By default, the AuxADCs are powered down and automatically
powered up when a conversion is initiated.
The two AuxADCs (AuxADC_A and AuxADC_B) can
monitor up to three system signals. AuxADC_A has multi-
plexed inputs that control whether pin AUX_ADC_A1 or pin
AUX_ADC_A2 is connected to the input of AuxADC_A. The
multiplexer is programmed through Register 0x22, Bit 1,
SelectA. By default, the register is low, which connects the
AUX_ADC_A2 pin to the input.
The full-scale AuxADC reference can be generated from the
analog supply (supply dependent), an internal reference, or
from an external applied reference. Table 10 shows the register
settings required to select the AuxADC full-scale reference.
By default, an internal reference provides a buffered full-scale
reference for both of the AuxADCs, which is equal to the
supply voltage for the AuxADCs (PLL_AVDD). A supply
independent 2.5 V or 3.0 V internal full-scale reference can be
enabled by writing to register AuxADC Ref Enable and
AuxADC Ref FS in Register 0x17. This internal reference is
based on the main Rx path ADC VREF voltage, so it requires
the main Rx path VREF to be enabled.
Another AuxADC full-scale reference option is an externally
supplied full-scale reference. The external reference can be
applied to either or both of the AuxADCs by setting the
appropriate bit(s) in Registers 0x22 and 0x17. Setting either or
both of these bits high disconnects the internal reference buffer
and enables the externally applied reference from the
AuxADC_Ref pin to the respective channel(s).
AD9861