AD9861 Analog Devices, AD9861 Datasheet - Page 42

• Manufacturer Part Number: AD9861
• Manufacturer: Analog Devices

Specifications of AD9861

• Resolution (bits): 10bit
• # Chan: 2
• Sample Rate: 80MSPS
• Interface: Par
• Analog Input Type: Diff-Uni
• Ain Range: 2 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

AD9861
PROGRAMMABLE REGISTERS
The AD9861 contains internal registers that are used to configure
the device. A serial port interface provides read/write access to
the internal registers. Single-byte or dual-byte transfers are
supported as well as MSB first or LSB first transfer formats. The
AD9861’s serial interface port can be configured as a single pin
I/O (SDIO) or as two unidirectional pins for in/out (SDIO/SDO).
The serial port is a flexible, serial communications port, allowing
easy interface to many industry-standard microcontrollers and
microprocessors.
General Operation of the Serial Interface
By default, the serial port accepts data in MSB first mode and
uses four pins: SEN, SCLK, SDIO, and SDO by default. SEN is a
serial clock enable pin; SCLK is the serial clock pin; SDIO is a
bidirectional data line; and SDO is a serial output pin.
SEN is an active low control gating read and write cycles. When
SEN is high, SDO and SDIO go into a high impedance state.
SCLK is used to synchronize SPI read and writes at a maximum
bit rate of 30 MHz. Input data is registered on the rising edge,
and output data transitions are registered on the falling edge.
During write operations, the registers are updated after the 16th
rising clock edge (and 24th rising clock edge for the dual-byte
case). Incomplete write operations are ignored.
SDIO is an input data only pin by default. Optionally, a 3-pin
interface may be configured using the SDIO for both input and
output operations and three-stating the SDO pin. Refer to the
SDIO BiDir bit in Register 0x00 (Table 18).
SDO
4-wire mode and is three-stated when SDIO is configured for
bidirectional operation.
There are two phases to a communication cycle with the AD9861.
Phase 1 is the instruction cycle, which is the writing of an
instruction byte into the AD9861, coincident with the first eight
SCLK rising edges. The instruction byte provides the AD9861
serial port controller with information regarding the data
transfer cycle, which is Phase 2 of the communication cycle. The
Phase 1 instruction byte defines whether the upcoming data
transfer is read or write, the number of bytes in the data transfer
(one or two), and the starting register address for the first byte
of the data transfer.
The first eight SCLK rising edges of each communication cycle
are used to write the instruction byte into the AD9861. The
remaining SCLK edges are for Phase 2 of the communication
is a serial output data pin used for readback operations in
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cycle. Phase 2 is the actual data transfer between the AD9861
and the system controller. Phase 2 of the communication cycle
is a transfer of one or two data bytes as determined by the
instruction byte. Normally, using one communication cycle in a
multibyte transfer is the preferred method; however, single byte
communication cycles are useful to reduce CPU overhead when
register access requires only one byte. An example of this is to
write the AD9861 power-down bits.
All data input to the AD9861 is registered on the rising edge of
SCLK. All data is driven out of the AD9861 on the falling edge
of SCLK.
Instruction Byte
The instruction byte contains the information shown in
Table 19, and the bits are described in detail after the table.
Table 19. Instruction Byte
MSB
R/nW
R/nW —Bit 7 of the instruction byte determines whether a read
or write data transfer will occur after the instruction byte write.
Logic high indicates a read operation. Logic low indicates a
write operation.
2/n1 Byte —Bit 6 of the instruction byte determines the number
of bytes to be transferred during the data transfer cycle of the
communication cycle. Logic high indicates a 2-byte transfer.
Logic low indicates a 1-byte transfer.
A5, A4, A3, A2, A1, A0 —Bits 5, 4, 3, 2, 1, and 0 of the
instruction byte determine which register is accessed during the
data transfer portion of the communication cycle. For 2-byte
transfers, this address is the starting byte address. The second
byte address is automatically decremented when the interface is
configured for MSB first transfers. For LSB first transfers, the
address of the second byte is automatically incremented.
Table 20. Serial Port Interface Timing
Maximum SCLK Frequency (f
Minimum SCLK High Pulse Width (t
Minimum SCLK Low Pulse Width (t
Maximum Clock Rise/Fall Time
Data to SCLK timing (t
Data Hold Time (t
D6
2/n1
Byte
DH
D5
A5
)
DS
)
D4
A4
SCLK
)
PWL
D3
A3
PWH
)
)
D2
A2
D1
A1
40 MHz
12.5 ns
12.5 ns
1 ms
12.5 ns
0 ns
LSB
A0