AD6645 Analog Devices, AD6645 Datasheet - Page 18

• Manufacturer Part Number: AD6645
• Description: 14-Bit, 80 MSPS/105 MSPS A/D Converter
• Manufacturer: Analog Devices

Specifications of AD6645

• Resolution (bits): 14bit
• # Chan: 1
• Sample Rate: 105MSPS
• Interface: Par
• Analog Input Type: Diff-Uni
• Ain Range: 2.2 V p-p
• Adc Architecture: Pipelined
• Pkg Type: QFP

AD6645
This limits the amount of dynamic current from the A/D
flowing back into the secondary of the transformer. The 50 Ω
impedance matching can also be incorporated on the secondary
side of the transformer, as shown in the evaluation board
schematic (see Figure 43).
In applications where dc coupling is required, a differential
output op amp, such as the AD8138, can be used to drive the
AD6645 (see Figure 41). The AD8138 op amp provides single-
ended-to-differential conversion, which reduces overall system
cost and minimizes layout requirements.
V
Power Supplies
Care should be taken when selecting a power source. The use of
linear dc supplies with rise times of <45 ms is highly recommended.
Switching supplies tend to have radiated components that can
be received by the AD6645. Decouple each of the power supply
pins as close to the package as possible using 0.1 μF chip capacitors.
The AD6645 has separate digital and analog power supply pins.
The analog supplies are AV
DV
the best performance is achieved when the supplies are separate
because the fast digital output swings can couple switching
currents back into the analog supplies. Note that AV
held within 5% of 5 V. The AD6645 is specified for DV
common supply for digital ASICs.
Digital Outputs
Care must be taken when designing the data receivers for the
AD6645. It is recommended that the digital outputs drive a
series resistor followed by a gate, such as the 74LCX574.
IN
CC
ANALOG INPUT
. Although analog and digital supplies can be tied together,
Figure 40. Transformer-Coupled Analog Input Circuit
499Ω
SIGNAL
499Ω
V
Figure 41. DC-Coupled Analog Input Circuit
OCM
R
AD8138
T
499Ω
C
5V
C
F
F
499Ω
ADT4-1WT
CC
and the digital supply pins are
25Ω
25Ω
0.1µF
R
R
S
S
AIN
AIN
AD6645
AIN
AIN
AD6645
VREF
CC
CC
DIGITAL
OUTPUTS
= 3.3 V, a
must be
Rev. D | Page 18 of 24
To minimize capacitive loading, there should be only one gate
on each output pin. An example of this is shown in the evaluation
board schematic of Figure 43. The digital outputs of the AD6645
have a constant output slew rate of 1 V/ns. A typical CMOS gate
combined with a PCB trace have a load of approximately 10 pF.
Therefore, as each bit switches, 10 mA (10 pF × 1 V ÷ 1 ns) of
dynamic current per bit flow in or out of the device. A full-scale
transition can cause up to 140 mA (14 bits × 10 mA/bit) of current
to flow through the output stages. Place the series resistors as close
to the AD6645 as possible to limit the amount of current that can
flow into the output stage. These switching currents are confined
between ground and DV
because they can add appreciably to the dynamic switching
currents of the AD6645. Note that extra capacitive loading
increases output timing and invalidates timing specifications.
Digital output timing is guaranteed for output loads up to
10 pF. Digital output states for given analog input levels are
shown in Table 8.
Grounding
For optimum performance, it is highly recommended that a
common ground be used between the analog and digital power
planes. The primary concern with splitting grounds is that
dynamic currents may be forced to travel significant distances
in the system before recombining back at the common source
ground. This can result in a large, undesirable ground loop. The
most common place for this to occur is on the digital outputs of
the ADC. Ground loops can contribute to digital noise being
coupled back onto the ADC front end. This can manifest itself
as either harmonic spurs, or very high-order spurious products
that can cause excessive spikes on the noise floor. This noise
coupling is less likely to occur at lower clock speeds because the
digital noise has more time to settle between samples. In general,
splitting the analog and digital grounds can frequently contribute
to undesirable EMI-RFI and should, therefore, be avoided.
Conversely, if not properly implemented, common grounding
can actually impose additional noise issues because the digital
ground currents ride on top of the analog ground currents in
close proximity to the ADC input. To further minimize the
potential for noise coupling, it is highly recommended that
multiple ground return traces/vias be placed such that the
digital output currents do not flow back toward the analog front
end but are routed quickly away from the ADC. This does not
require a split in the ground plane and can be accomplished by
simply placing substantial ground connections directly back to
the supply at a point between the analog front end and the
digital outputs. In addition, the judicious use of ceramic chip
capacitors between the power supply and ground planes helps
to suppress digital noise. The layout should incorporate enough
bulk capacitance to supply the peak current requirements
during switching periods.
CC
. Standard TTL gates should be avoided