AD7864 Analog Devices, AD7864 Datasheet - Page 11

• Manufacturer Part Number: AD7864
• Description: High Speed, Low Power, 4-channel Simultaneous Sampling, 12-Bit ADC
• Manufacturer: Analog Devices

Specifications of AD7864

• Resolution (bits): 12bit
• # Chan: 4
• Sample Rate: 520kSPS
• Interface: Par
• Analog Input Type: SE-Bip,SE-Uni
• Ain Range: Bip 10V,Bip 2.5V,Bip 5.0V,Uni 2.5V,Uni 5.0V
• Adc Architecture: SAR
• Pkg Type: QFP

THEORY OF OPERATION
CONVERTER DETAILS
The AD7864 is a high speed, low power, 4-channel simultaneous
sampling 12-bit ADC that operates from a single 5 V supply.
The part contains a 1.65 μs successive approximation ADC, four
track-and-hold amplifiers, an internal 2.5 V reference, and a
high speed parallel interface. There are four analog inputs that
can be simultaneously sampled, thus preserving the relative
phase information of the signals on all four analog inputs.
Thereafter, conversions are completed on the selected subset of
the four channels. The part accepts an analog input range of
±10 V or ±5 V (AD7864-1), ±2.5 V (AD7864-3), and 0 V to
+2.5 V or 0 V to +5 V (AD7864-2). Overvoltage protection on
the analog inputs of the part allows the input voltage to go to
±20 V, (AD7864-1 ±10 V range), −7 V or +20 V (AD7864-1
±5 V range), −1 V to +20 V (AD7864-2), and −7 V to +20 V
(AD7864-3), without causing damage. The AD7864 has two
operating modes: reading-between-conversions and reading-
after-the-conversion sequence. These modes are discussed in
more detail in the Timing and Control section.
A conversion is initiated on the AD7864 by pulsing the CONVST
input. On the rising edge of CONVST, all four on-chip track-
and-holds are placed into hold simultaneously and the conversion
sequence is started on all the selected channels. Channel selection
is made via the SL1 to SL4 pins if H/S SEL is Logic 0 or via the
channel select register if H/S SEL is Logic 1—see the
Conversion Sequence
programmed via the bidirectional data lines (DB0 to DB3) and
a standard write operation. The selected conversion sequence is
latched on the rising edge of
selection only takes effect once a new conversion sequence is
initiated. The BUSY output signal is triggered high on the rising
edge of CONVST and remains high for the duration of the conver-
sion sequence. The conversion clock for the part is generated
internally using a laser trimmed, clock oscillator circuit.
There is also the option of using an external clock, by tying the
INT/EXT CLK pin logic high, and applying an external clock to
the CLKIN pin. However, the optimum throughput is obtained
by using the internally generated clock—see the
External Clock
each conversion in the conversion sequence. The BUSY signal
indicates the end of the full conversion sequence, and at this
time, all four track and holds return to tracking mode. The
conversion results can be read either at the end of the full
conversion sequence (indicated by BUSY going low), or as each
result becomes available (indicated by EOC going low). Data is
read from the part via a 12-bit parallel data bus with standard
CS and RD signals—see the
section. The
section. The channel select register is
Timing and Control
EOC signal indicates the end of
CONVST, therefore, changing a
Using an
section.
Selecting a
Rev. D | Page 11 of 28
Conversion time for each channel of the AD7864 is 1.65 μs, and
the track-and-hold acquisition time is 0.35 μs. To obtain optimum
performance from the part, the read operation should not occur
during a channel conversion or during the 100 ns prior to the
next CONVST rising edge. This allows the part to operate at
throughput rates up to 130 kHz for all four channels and
achieve data sheet specifications.
Track-and-Hold Amplifiers
The track-and-hold amplifiers on the AD7864 allow the ADCs
to accurately convert an input sine wave of full-scale amplitude
to 12-bit accuracy. The input bandwidth of the track-and-hold
is greater than the Nyquist rate of the ADC even when the ADC
is operated at its maximum throughput rate of 500 kSPS (that is,
the track-and-hold can handle input frequencies in excess of
250 kHz).
The track-and-hold amplifiers acquire input signals to 12-bit
accuracy in less than 350 ns. The operation of the track-and-
holds are essentially transparent to the user. The four track-and-
hold amplifiers sample their respective input channels simulta-
neously, on the rising edge of CONVST. The aperture time for
the track-and-holds (that is, the delay time between the external
CONVST signal and the track-and-hold actually going into hold)
is typically 15 ns and, more importantly, is well matched across
the four track-and-holds on one device as well as being well
matched from device to device. This allows the relative phase
information between different input channels to be accurately
preserved. It also allows multiple AD7864s to sample more than
four channels simultaneously. At the end of a conversion sequence,
the part returns to its tracking mode. The acquisition time of
the track-and-hold amplifiers begin at this point.
Reference
The AD7864 contains a single reference pin, labeled V
V
or it serves as the reference source for the part by connecting
V
2.5 V reference voltage. Errors in the reference source result in
gain errors in the transfer function of the AD7864 and adds to
the specified full-scale errors on the part. On the AD7864-1 and
AD7864-3, it also results in an offset error injected in the attenuator
stage; see Figure 4 and Figure 6.
The AD7864 contains an on-chip 2.5 V reference. To use this
reference as the reference source for the AD7864, simply con-
nect a 0.1 μF disk ceramic capacitor from the V
The voltage that appears at this pin is internally buffered before
being applied to the ADC. If this reference is used externally to
the AD7864, it should be buffered because the part has a FET
switch in series with the reference output resulting in a 6 kΩ
REF
REF
pin provides access to the 2.5 V reference within the part,
to an external 2.5 V reference. The part is specified with a
REF
pin to AGND.
AD7864
REF
. The