AD7864 Analog Devices, AD7864 Datasheet - Page 17

• Manufacturer Part Number: AD7864
• Description: High Speed, Low Power, 4-channel Simultaneous Sampling, 12-Bit ADC
• Manufacturer: Analog Devices

Specifications of AD7864

• Resolution (bits): 12bit
• # Chan: 4
• Sample Rate: 520kSPS
• Interface: Par
• Analog Input Type: SE-Bip,SE-Uni
• Ain Range: Bip 10V,Bip 2.5V,Bip 5.0V,Uni 2.5V,Uni 5.0V
• Adc Architecture: SAR
• Pkg Type: QFP

Successive read operations access the remaining conversion
results in an ascending channel order. Each read operation
increments the output data register pointer. The read operation
that accesses the last conversion result causes the output data
register pointer to be reset so that the next read operation accesses
the first conversion result again. This is shown in Figure 10,
wherein the fifth read after BUSY goes low accessing the result
of the conversion on V
a circular buffer in which the conversion results are continually
accessible. The FRSTDATA signal goes high when the first
conversion result is available.
Data is enabled onto the data bus (DB0 to DB11) using CS and
RD. Both CS and RD have the same functionality as described
in the previous section. There are no restrictions or performance
implications associated with the position of the read operations
after BUSY goes low. The only restriction is that there is minimum
time between read operations. Notice that the quiet time must
be allowed before the start of the next conversion.
USING AN EXTERNAL CLOCK
The logic input INT/EXT CLK allows the user to operate the
AD7864 using the internal clock oscillator or an external clock.
To achieve optimum performance on the AD7864, use the internal
clock. The highest external clock frequency allowed is 5 MHz.
FRSTDATA
IN1
CONVST
. Thus, the output data registers act as
BUSY
EOC
CLK
RD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1 2
FIRST CONVERSION
COMPLETE
Figure 11. Using an External Clock
Rev. D | Page 17 of 28
This means a conversion time of 2.6 μs compared to 1.65 μs
when using the internal clock. In some instances, however, it
may be useful to use an external clock when high throughput
rates are not required. For example, two or more AD7864s can
be synchronized by using the same external clock for all
devices. In this way, there is no latency between output logic
signals like EOC due to differences in the frequency of the
internal clock oscillators.
outputs are synchronized to the CLK signal. Each conversion
requires 14 clocks. The output data register pointer is reset to
point to the first register location on the falling edge of the 12th
clock cycle of the first conversion in the conversion sequence—
see the
point, the logic output FRSTDATA goes logic high. The result of
the first conversion transfers to the output data registers on the
falling edge of the 13th clock cycle. The FRSTDATA signal is
reset on the falling edge of the 13th clock cycle of the next
conversion, that is, when the result of the second conversion is
transferred to its output data register. As mentioned previously,
the pointer is incremented by the rising edge of the
the result of the next conversion is available. The EOC signal
goes logic low on the falling edge of the 13th clock cycle and is
reset high again on the falling edge of the 14th clock cycle.
LAST CONVERSION
COMPLETE
Accessing the Output Data Registers
Figure 11
13 14
shows how the various logic
section. At this
RD signal if
AD7864