AD5363 Analog Devices, AD5363 Datasheet - Page 16

no-image

AD5363

Manufacturer Part Number
AD5363
Description
8-Channel, 14-Bit, Serial Input, Voltage-Output DAC
Manufacturer
Analog Devices
Datasheet

Specifications of AD5363

Resolution (bits)
14bit
Dac Settling Time
20µs
Single-supply
No
Dac Type
Voltage Out
Dac Input Format
Ser,SPI

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AD5363BSTZ
Manufacturer:
ADI
Quantity:
329
Part Number:
AD5363BSTZ
Manufacturer:
Analog Devices Inc
Quantity:
10 000
Part Number:
AD5363BSTZ-REEL
Manufacturer:
Analog Devices Inc
Quantity:
10 000
AD5362/AD5363
THEORY OF OPERATION
DAC ARCHITECTURE
The AD5362/AD5363 contain eight DAC channels and eight
output amplifiers in a single package. The architecture of a
single DAC channel consists of a 16-bit (AD5362) or 14-bit
(AD5363) resistor-string DAC followed by an output buffer
amplifier. The resistor-string section is simply a string of resistors,
of equal value, from VREF0 or VREF1 to AGND. This type of
architecture guarantees DAC monotonicity. The 16-bit (AD5362)
or 14-bit (AD5363) binary digital code loaded to the DAC
register determines at which node on the string the voltage is
Table 7. AD5362/AD5363 Registers
Register Name
X1A (Group) (Channel)
X1B (Group) (Channel)
M (Group) (Channel)
C (Group) (Channel)
X2A (Group) (Channel)
X2B (Group) (Channel)
DAC (Group) (Channel)
OFS0
OFS1
Control
Monitor
GPIO
A/B Select 0
A/B Select 1
Table 8. AD5362/AD5363 Input Register Default Values
Register Name
X1A, X1B
M
C
OFS0, OFS1
Control
A/B Select 0 and A/B Select 1
Word Length in Bits
16 (14)
16 (14)
16 (14)
16 (14)
16 (14)
16 (14)
14
14
5
6
2
8
8
AD5362 Default Value
0x8000
0xFFFF
0x8000
0x2000
0x00
0x00
Description
Input Data Register A, one for each DAC channel.
Input Data Register B, one for each DAC channel.
Gain trim registers, one for each DAC channel.
Offset trim registers, one for each DAC channel.
Output Data Register A, one for each DAC channel. These registers store the final,
calibrated DAC data after gain and offset trimming. They are not readable or directly
writable.
Output Data Register B, one for each DAC channel. These registers store the final,
calibrated DAC data after gain and offset trimming. They are not readable or directly
writable.
Data registers from which the DACs take their final input data. The DAC registers are
updated from the X2A or X2B registers. They are not readable or directly writable.
Offset DAC 0 data register: sets offset for Group 0.
Offset DAC 1 data register: sets offset for Group 1.
Bit 4 = overtemperature indicator.
Bit 3 = PEC error flag.
Bit 2 = A/B select.
Bit 1 = thermal shutdown.
Bit 0 = software power-down.
Bit 5 = monitor enable.
Bit 4 = monitor DACs or monitor MON_INx pin.
Bit 3 to Bit 0 = monitor selection control.
Bit 1 = GPIO configuration.
Bit 0 = GPIO data.
Bits [3:0] in this register determine whether a DAC in Group 0 takes its data from
Register X2A or Register X2B (0 = X2A, 1 = X2B).
Bits [3:0] in this register determine whether a DAC in Group 1 takes its data from
Register X2A or Register X2B (0 = X2A, 1 = X2B).
Rev. A | Page 16 of 28
tapped off before being fed into the output amplifier. The output
amplifier multiplies the DAC output voltage by 4. The nominal
output span is 12 V with a 3 V reference and 20 V with a 5 V
reference.
CHANNEL GROUPS
The eight DAC channels of the AD5362/AD5363 are arranged
into two groups of four channels. The four DACs of Group 0
derive their reference voltage from VREF0. The four DACs of
Group 1 derive their reference voltage from VREF1. Each group
has its own signal ground pin.
0x2000
AD5363 Default Value
0x3FFF
0x2000
0x2000
0x00
0x00

Related parts for AD5363