AD5373 Analog Devices, AD5373 Datasheet

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AD5373

Manufacturer Part Number
AD5373
Description
32-Channel, 14-Bit, Serial Input, Voltage-Output DAC
Manufacturer
Analog Devices
Datasheet

Specifications of AD5373

Resolution (bits)
14bit
Dac Update Rate
540kSPS
Dac Settling Time
20µs
Max Pos Supply (v)
+16.5V
Single-supply
No
Dac Type
Voltage Out
Dac Input Format
Ser,SPI

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FEATURES
32-channel DAC in a 64-lead LQFP and 64-lead LFCSP
AD5372/AD5373
Maximum output voltage span of 4 × VREF (20 V)
Nominal output voltage range of −4 V to +8 V
Multiple, independent output voltage spans available
System calibration function allowing user-programmable
Channel grouping and addressing features
Thermal shutdown function
DSP/microcontroller-compatible serial interface
SPI serial interface
1
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
Protected by U.S. Patent No. 5,969,657.
offset and gain
RESET
SYNC
SCLK
BUSY
SDO
CLR
SDI
INTERFACE
AD5372/
AD5373
CONTROL
REGISTER
MACHINE
SERIAL
STATE
1
guaranteed monotonic to 16/14 bits
n
8
n
n
n
n
n
n
8
n
n
n
n
n
n
X1 REGISTER
X1 REGISTER
X1 REGISTER
X1 REGISTER
M REGISTER
C REGISTER
M REGISTER
C REGISTER
M REGISTER
C REGISTER
M REGISTER
C REGISTER
A/B SELECT
A/B SELECT
REGISTER
REGISTER
n = 16 FOR AD5372
n = 14 FOR AD5373
AGND DGND
8
n
n
8
n
n
n
n
n
n
n
n
n
n
TO
MUX 2s
TO
MUX 2s
FUNCTIONAL BLOCK DIAGRAM
n
n
n
n
X2A REGISTER
X2B REGISTER
X2A REGISTER
X2B REGISTER
X2A REGISTER
X2B REGISTER
X2A REGISTER
X2B REGISTER
Figure 1.
Serial Input, Voltage Output DAC
ARE IDENTICAL TO GROUP 1
GROUP 2 TO GROUP 3
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
2.5 V to 5.5 V JEDEC-compliant digital levels
Digital reset (RESET)
Clear function to user-defined SIGGNDx
Simultaneous update of DAC outputs
APPLICATIONS
Level setting in automatic test equipment (ATE)
Variable optical attenuators (VOA)
Optical switches
Industrial control systems
Instrumentation
14
14
LDAC
n
n
n
n
REGISTER
REGISTER
REGISTER
REGISTER
REGISTER
REGISTER
DAC 0
DAC 7
DAC 0
DAC 7
OFS0
OFS1
32-Channel, 16-/14-Bit,
n
n
n
n
n
n
VREF1 SUPPLIES
GROUP 1 TO GROUP 3
©2007–2011 Analog Devices, Inc. All rights reserved.
SIGGND2
OFFSET
OFFSET
DAC 0
DAC 1
DAC 0
DAC 7
DAC 0
DAC 7
BUFFER
BUFFER
SIGGND3
AD5372/AD5373
BUFFER
BUFFER
OUTPUT BUFFER
DOWN CONTROL
OUTPUT BUFFER
DOWN CONTROL
OUTPUT BUFFER
OUTPUT BUFFER
DOWN CONTROL
DOWN CONTROL
AND POWER-
AND POWER-
AND POWER-
AND POWER-
GROUP 0
GROUP 1
www.analog.com
VREF0
VOUT0
VOUT1
VOUT2
VOUT3
VOUT4
VOUT5
VOUT6
VOUT7
SIGGND0
VREF1
VOUT8
VOUT9
VOUT10
VOUT11
VOUT12
VOUT13
VOUT14
VOUT15
SIGGND1
VOUT16
TO
VOUT31

Related parts for AD5373

AD5373 Summary of contents

Page 1

... Multiple, independent output voltage spans available System calibration function allowing user-programmable offset and gain Channel grouping and addressing features Thermal shutdown function DSP/microcontroller-compatible serial interface SPI serial interface AGND DGND FOR AD5372 n CONTROL FOR AD5373 REGISTER 8 A/B SELECT REGISTER n X1 REGISTER n M REGISTER n C REGISTER ...

Page 2

... Changes to Absolute Maximum Ratings Section..........................9 Changes to Pin Configuration and Function Descriptions Section.............................................................................................. 10 Changes to Reset Function Section.............................................. 18 12/07—Rev Rev. A Changes to Table 3.............................................................................6 Changes to AD5373 Transfer Function Section......................... 16 Changes to Calibration Section .................................................... 17 Changes to Table 8.......................................................................... 18 Changes to Register Update Rates Section.................................. 20 Changes to Ordering Guide .......................................................... 25 8/07—Revision 0: Initial Version Rev Page   ...

Page 3

... V AD5379 14 ±8.75 V The AD5372/AD5373 have a high speed serial interface that is compatible with SPI, QSPI™, MICROWIRE™, and DSP inter- face standards and can handle clock speeds MHz. The DAC registers are updated on reception of new data. All the outputs can be updated simultaneously by taking the LDAC input low ...

Page 4

... DIGITAL OUTPUTS (SDO, BUSY) Output Low Voltage Output High Voltage (SDO) SDO High Impedance Leakage Current High Impedance Output Capacitance = −16 −8 V; VREF0 = VREF1 = 3 V; AGND = DGND = SIGGNDx = AD5372 1 AD5373 1 B Version B Version Unit 16 14 Bits ±4 ±1 LSB max ± ...

Page 5

... VREF0, VREF1 = 2 V p-p, 1 kHz 10 nV-s typ 0.2 nV-s typ 0.02 nV-s typ Effect of input bus activity on DAC output under test 250 nV/√Hz typ VREF0 = VREF1 = 0 V Rev Page AD5372/AD5373 2 Test Conditions/Comments GND Outputs unloaded, DAC outputs = 0 V Outputs unloaded, DAC outputs = full scale ...

Page 6

... AD5372/AD5373 TIMING CHARACTERISTICS open circuit; gain (M), offset (C), and DAC offset registers at default values; all specifications T L Table 4. SPI Interface Parameter Limit MIN MAX ...

Page 7

... RESET VOUTx BUSY 1 LDAC ACTIVE DURING BUSY. 2 LDAC ACTIVE AFTER BUSY DB0 Figure 4. SPI Write Timing Rev Page AD5372/AD5373 ...

Page 8

... AD5372/AD5373 SCLK SYNC SDI DB23 SDO DB0 DB23 INPUT WORD SPECIFIES REGISTER TO BE READ DB0 DB23 SELECTED REGISTER DATA CLOCKED OUT LSB FROM PREVIOUS WRITE Figure 5. SPI Read Timing OUTPUT VOLTAGE 8V ACTUAL TRANSFER FUNCTION IDEAL TRANSFER FUNCTION 0 DAC CODE ...

Page 9

... 0 ESD CAUTION −0 0 −0 +5 − − −0 +0.3 V −40°C to +85°C −65°C to +150°C 130°C 25.5°C/W 45.5°C/W 230°C 10 sec to 40 sec Rev Page AD5372/AD5373 ...

Page 10

... Serial Data Input. Data must be valid on the falling edge of SCLK. Rev Page PIN 1 47 INDICATOR AD5372/AD5373 41 TOP VIEW (Not to Scale Figure 8 ...

Page 11

... Ground for All Analog Circuitry. The AGND pin should be connected to the AGND plane. Load DAC Logic Input (Active Low). See the BUSY and LDAC Functions section for more information. Asynchronous Clear Input (Level Sensitive, Active Low). See the Clear Function section for more information. Rev Page AD5372/AD5373 ...

Page 12

... AD5372/AD5373 TYPICAL PERFORMANCE CHARACTERISTICS –1 –2 0 16384 32768 DAC CODE Figure 9. Typical AD5372 INL Plot 1.0 0.5 0 –0.5 –1 TEMPERATURE (°C) Figure 10. Typical INL Error vs. Temperature 25° –15V +15V DD VREFx = +4.096V –0.01 –0. TIME (µs) Figure 11. Analog Crosstalk Due to LDAC ...

Page 13

... TEMPERATURE (°C) Figure 16 vs. Temperature + Rev Page AD5372/AD5373 V = –15V +15V 25°C A 12.8 13.0 13.2 13.4 I (mA) DD Figure 17. Typical I Distribution 25°C A 0.35 0.40 0.45 0.50 DI (mA) CC Figure 18. Typical DI Distribution ...

Page 14

... It is specified as the area of the glitch in nV- measured by toggling the DAC register data between 0x7FFF and 0x8000 (AD5372) or 0x1FFF and 0x2000 (AD5373). Channel-to-Channel Isolation Channel-to-channel isolation refers to the proportion of input signal from the reference input of one DAC that appears at the output of another DAC operating from another reference ...

Page 15

... The nominal output span with reference and 20 V with reference. CHANNEL GROUPS The 32 DAC channels of the AD5372/AD5373 are arranged into four groups of eight channels. The eight DACs of Group 0 derive their reference voltage from VREF0. Group 1 to Group 3 derive their reference voltage from VREF1 ...

Page 16

... Group 0 or Group 1 to Group unipolar positive, unipolar negative, or bipolar, either symmetrical or asymmetrical about 0 V. The DACs in the AD5372/AD5373 are factory trimmed with the offset DACs set at their default values. This gives the best offset and gain performance for the default output range and span. ...

Page 17

... VREF = (VOUT If the offset and gain features of the AD5372/AD5373 are used, the required output range is slightly different. The selected output range should take into account the system offset and gain errors that need to be trimmed out. Therefore, the selected output range should be larger than the actual required range ...

Page 18

... Use a combination of these two approaches. CALIBRATION The user can perform a system calibration on the AD5372/ AD5373 to reduce gain and offset errors to below 1 LSB. This reduction is achieved by calculating new values for the M and C registers and reprogramming them. The M and C registers should not be programmed until both ...

Page 19

... These limitations can be overcome by increasing the reference value. With reference span is achieved. The ideal voltage range, for the AD5372 or the AD5373, is − Using a +3.1 V reference increases the range to −4.133 V to +8.2667 V. Clearly, in this case, the offset and gain errors are insignificant, and the M and C registers can be used to raise the negative voltage to − ...

Page 20

... To indicate that the AD5372/AD5373 have entered thermal shutdown mode, Bit 4 of the control register is set to 1. The AD5372/AD5373 remain in thermal shutdown mode, even if the die temperature falls, until Bit 1 in the control register is cleared to 0. ...

Page 21

... LDAC . The serial word (see Table (AD5372 (AD5373) of these bits are data bits; six bits are address bits; and two bits are mode bits that determine what is done with the data. Two bits are reserved on the AD5373. The serial interface works with both a continuous and a burst (gated) serial clock ...

Page 22

... CHANNEL ADDRESSING AND SPECIAL MODES If the mode bits are not 00, the data-word D15 to D0 (AD5372) or D13 to D0 (AD5373) is written to the device. Address Bit A5 to Address Bit A0 determine which channels are written to, and the mode bits determine to which register (X1A, X1B the data is written, as shown in Table 13 and Table 14 ...

Page 23

... Channel 0 = 001000 to Channel 31 = 100111 Rev Page AD5372/AD5373 I10 F10 Register Read X1A register X1B register C register M register 0 1 Control register 1 0 ...

Page 24

... RCLKx) are also connected. The user can write to the AD5372/AD5373 by writing to the transmit register of the ADSP-21065L. A read operation can be accom- plished by first writing to the AD5372/AD5373 to tell the part that a read operation is required. A second write operation with an NOP instruction causes the data to be read from the AD5372/AD5373 ...

Page 25

... COPLANARITY VIEW A 0.50 BSC LEAD PITCH COMPLIANT TO JEDEC STANDARDS MS-026-BCD Figure 25. 64-Lead Low Profile Quad Flat Package [LQFP] (ST-64-2) Dimensions shown in millimeters Rev Page AD5372/AD5373 0.60 MAX PIN 1 INDICATOR 64 1 7.25 EXPOSED PAD 7.10 SQ (BOTTOM VIEW) 6. 0.25 MIN 7.50 REF FOR PROPER CONNECTION OF ...

Page 26

... AD5372BCPZ-RL7 −40°C to +85°C AD5373BSTZ −40°C to +85°C AD5373BSTZ-REEL −40°C to +85°C AD5373BCPZ −40°C to +85°C AD5373BCPZ-RL7 −40°C to +85°C EVAL-AD5372EBZ EVAL-AD5373EBZ RoHS Compliant Part. Package Description 64-Lead Low Profile Quad Flat Package (LQFP) 64-Lead Low Profile Quad Flat Package (LQFP) ...

Page 27

... NOTES Rev Page AD5372/AD5373 ...

Page 28

... AD5372/AD5373 NOTES ©2007–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05815-0-7/11(C) Rev Page ...

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