ADUC7126 Analog Devices, ADUC7126 Datasheet - Page 15

• Manufacturer Part Number: ADUC7126
• Description: Precision Analog Microcontroller, 12-Bit Analog I/O, Large Memory, ARM7TDMI MCU with Enhanced IRQ Handler
• Manufacturer: Analog Devices

Specifications of ADUC7126

• Mcu Core: ARM7 TDMI
• Mcu Speed (mips): 40
• Gpio Pins: 40
• Adc # Channels: 16
• Other: PWM

Pin No.
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
Mnemonic
XCLKO
XCLKI
BM/P0.0/CMP
DGND
LV
IOV
IOGND
P4.6/PLAO[14]
P4.7/PLAO[15]
P0.6/T1/MRST/PLAO[3]
TCK
TDO
P3.0/PWM0/PLAI[8]
P3.1/PWM1/PLAI[9]
P3.2/PWM2/PLAI[10]
P3.3/PWM3/PLAI[11]
P0.3/TRST/ADC
P3.4/PWM4/PLAI[12]
P3.5/PWM5/PLAI[13]
RST
IRQ0/P0.4/PWM
DD
DD
OUT
BUSY
TRIP
/PLAI[7]
/PLAO[1]
Description
Output from the Crystal Oscillator Inverter.
Input to the Crystal Oscillator Inverter and Input to the Internal Clock Generator
Circuits.
Multifunction I/O Pin.
Boot mode (BM). The ADuC7124 enters download mode if BM is low at reset and
executes code if BM is pulled high at reset through a 1 kΩ resistor.
General-Purpose Input and Output Port 0.0 (P0.0).
Voltage Comparator Output (CMP
Programmable Logic Array Input Element 7 (PLAI[7]).
Ground for Core Logic.
2.6 V Output of the On-Chip Voltage Regulator. This output must be connected to a
0.47 µF capacitor to DGND only.
3.3 V Supply for GPIO and Input of the On-Chip Voltage Regulator.
Ground for GPIO. Typically connected to DGND.
General-Purpose Input and Output Port 4.6 (P4.6).
Programmable Logic Array Output Element 14 (PLAO[14]).
General-Purpose Input and Output Port 4.7 (P4.7).
Programmable Logic Array Output Element 15 (PLAO[15]).
Multifunction Pin, Driven Low After Reset.
General-Purpose Output Port 0.6 (P0.6).
Timer1 Input (T1).
Power-On Reset Output (MRST).
Programmable Logic Array Output Element 3 (PLAO[3]).
JTAG Test Port Input, Test Clock. Debug and download access.
JTAG Test Port Output, Test Data Out.
General-Purpose Input and Output Port 3.0 (P3.0).
PWM Phase 0 (PWM0).
Programmable Logic Array Input Element 8 (PLAI[8]).
General-Purpose Input and Output Port 3.1 (P3.1).
PWM Phase 1 (PWM1).
Programmable Logic Array Input Element 9 (PLAI[9]).
General-Purpose Input and Output Port 3.2 (P3.2).
PWM Phase 2 (PWM2).
Programmable Logic Array Input Element 10 (PLAI[10]).
General-Purpose Input and Output Port 3.3 (P3.3).
PWM Phase 3 (PWM3).
Programmable Logic Array Input Element 11 (PLAI[11]).
General-Purpose Input and Output Port 0.3 (P0.3).
JTAG Test Port Input, Test Reset (TRST). JTAG reset input. Debug and download access. If
this pin is held low, JTAG access is not possible because the JTAG interface is held in reset
and P0.1/P0.2/P0.3 are configured as GPIO pins.
ADC
General-Purpose Input and Output Port 3.4 (P3.4).
PWM Phase 4 (PWM4).
Programmable Logic Array Input 12 (PLAI[12]).
General-Purpose Input and Output Port 3.5 (P3.5).
PWM Phase 5 (PWM5).
Programmable Logic Array Input Element 13 (PLAI[13]).
Reset Input, Active Low.
Multifunction I/O Pin.
External Interrupt Request 0, Active High (IRQ0).
General-Purpose Input and Output Port 0.4 (P0.4).
PWM Trip External Input (PWM
Programmable Logic Array Output Element 1 (PLAO[1]).
BUSY
Rev. B | Page 15 of 104
Signal Output (ADC
BUSY
).
TRIP
).
OUT
)
ADuC7124/ADuC7126