ADUC7126 Analog Devices, ADUC7126 Datasheet - Page 51

• Manufacturer Part Number: ADUC7126
• Description: Precision Analog Microcontroller, 12-Bit Analog I/O, Large Memory, ARM7TDMI MCU with Enhanced IRQ Handler
• Manufacturer: Analog Devices

Specifications of ADUC7126

• Mcu Core: ARM7 TDMI
• Mcu Speed (mips): 40
• Gpio Pins: 40
• Adc # Channels: 16
• Other: PWM

OTHER ANALOG PERIPHERALS
DAC
The ADuC7124/ADuC7126 incorporate two, or four, 12-bit
voltage output DACs on chip, depending on the model. Each
DAC has a rail-to-rail voltage output buffer capable of driving
5 kΩ/100 pF.
Each DAC has three selectable ranges: 0 V to V
band gap 2.5 V reference), 0 V to DAC
DAC
The signal range is 0 V to AV
MMRs Interface
Each DAC is independently configurable through a control
register and a data register. These two registers are identical for
the four DACs. Only DAC0CON (see Table 63) and DAC0DAT
(see Table 65) are described in detail in this section.
Table 62. DACxCON Registers
Name
DAC0CON
DAC1CON
DAC2CON
DAC3CON
Table 63. DAC0CON MMR Bit Descriptions
Bit
[7:6]
5
4
3
2
[1:0]
Table 64. DACxDAT Registers
Name
DAC0DAT
DAC1DAT
DAC2DAT
DAC3DAT
REF
Value
00
01
10
11
is equivalent to an external reference for the DAC.
Address
0xFFFF0600
0xFFFF0608
0xFFFF0610
0xFFFF0618
Address
0xFFFF0604
0xFFFF060C
0xFFFF0614
0xFFFF061C
Name
DACCLK
DACCLR
Description
Reserved.
DAC update rate.
Set by the user to update the DAC
using Timer1.
Cleared by the user to update the
DAC using HCLK (core clock).
DAC clear bit.
Set by the user to enable normal
DAC operation.
Cleared by the user to reset the data
register of the DAC to 0.
Reserved. This bit should be left at 0.
Reserved. This bit should be left at 0.
DAC range bits.
Power-down mode. The DAC output
is in tristate.
0 V to DAC
0 V to V
0 V to AV
DD
.
Default Value
0x00
0x00
0x00
0x00
Default Value
0x00000000
0x00000000
0x00000000
0x00000000
REF
DD
(2.5 V) range.
REF
REF
range.
range.
, and 0 V to AV
REF
(internal
Access
R/W
R/W
R/W
R/W
Access
R/W
R/W
R/W
R/W
DD
.
Rev. B | Page 51 of 104
Table 65. DAC0DAT MMR Bit Descriptions
Bit
[31:28]
[27:16]
[15:0]
Using the DACs
The on-chip DAC architecture consists of a DAC resistor string
followed by an output buffer amplifier. The functional equivalent
is shown in Figure 41.
As illustrated in Figure 41, the reference source for each DAC is
user selectable in software. It can be either AV
In 0 V-to-AV
from 0 V to the voltage at the AV
the DAC output transfer function spans from 0 V to the voltage at
the DAC
function spans from 0 V to the internal 2.5 V reference, V
The DAC output buffer amplifier features a true, rail-to-rail
output stage implementation. This means that, when unloaded,
each output is capable of swinging to within less than 5 mV of
both AV
(when driving a 5 kΩ resistive load to ground) is guaranteed
through the full transfer function except the 0 to 100 codes,
and, in 0 V-to-AV
Linearity degradation near ground and V
ration of the output amplifier, and a general representation of its
effects (neglecting offset and gain error) is illustrated in Figure 42.
The dotted line in Figure 42 indicates the ideal transfer function,
and the solid line represents what the transfer function may
look like with endpoint nonlinearities due to saturation of the
output amplifier. Note that Figure 42 represents a transfer function
in 0 V-to-AV
mode (with V
ity is similar. However, the upper portion of the transfer function
follows the ideal line right to the end (V
showing no signs of endpoint linearity errors.
DD
REF
and ground. Moreover, the DAC linearity specification
pin. In 0 V-to-V
DAC
DD
DD
REF
AV
V
REF
REF
mode, the DAC output transfer function spans
mode only. In 0 V-to-V
DD
< AV
DD
Description
Reserved.
12-bit data for DAC0.
Reserved.
mode only, Code 3995 to Code 4095.
DD
Figure 41. DAC Structure
or DAC
R
R
R
R
R
REF
ADuC7124/ADuC7126
mode, the DAC output transfer
REF
DD
< AV
pin. In 0 V-to-DAC
REF
REF
DD
in this case, not AV
), the lower nonlinear-
DD
or 0 V-to-DAC
is caused by satu-
DD
, V
DAC0
REF
, or DAC
REF
REF
mode,
REF
.
DD
REF
),
.