ADUC7126 Analog Devices, ADUC7126 Datasheet - Page 75

• Manufacturer Part Number: ADUC7126
• Description: Precision Analog Microcontroller, 12-Bit Analog I/O, Large Memory, ARM7TDMI MCU with Enhanced IRQ Handler
• Manufacturer: Analog Devices

Specifications of ADUC7126

• Mcu Core: ARM7 TDMI
• Mcu Speed (mips): 40
• Gpio Pins: 40
• Adc # Channels: 16
• Other: PWM

Bit
5
4
3
2
1
0
I
Name:
Address:
Default Value:
Access:
Function:
Table 110. I2CxSSTA MMR Bit Descriptions
Bit
15
14
13
2
C Slave Status Registers
Name
I2CSETEN
I2CGCCLR
I2CHGCEN
I2CGCEN
ADR10EN
I2CSEN
Name
I2CSTA
I2CREPS
I2C0SSTA, I2C1SSTA
0xFFFF082C, 0xFFFF092C
0x0000, 0x0000
Read only
This 16-bit MMR is the I
Description
I
Setting this bit enables a transmit request interrupt just after the positive edge of SCL during the read bit
transmission.
Clear this bit to enable a transmit request interrupt just after the negative edge of SCL during the read bit
transmission.
I
Writing a 1 to this bit clears the general call status (I2CGC) and ID (I2CGCID[1:0]) bits in the I2CxSSTA register.
Clear this bit at all other times.
I
When this bit and Bit 2 are set, and having received a general call (Address 0x00) and a data byte, the device
checks the contents of the I2CxALT against the receive register. If the contents match, the device has received a
hardware general call. This is used if a device needs urgent attention from a master device without knowing
which master it needs to turn to. This is a broadcast message to all master devices on the bus. The ADuC7124/
ADuC7126 watch for these addresses. The device that requires attention embeds its own address into the
message. All masters listen, and the one that can handle the device contacts its slave and acts appropriately.
The LSB of the I2CxALT register should always be written to 1, as per the I
Set this bit and I2CGCEN to enable hardware general call recognition in slave mode.
Clear this bit to disable recognition of hardware general call commands.
I
Set this bit to enable the slave device to acknowledge an I
recognizes a data bit. If it receives a 0x06 (reset and write programmable part of the slave address by hard-
ware) as the data byte, the I
be used to reset an entire I
hardware) as the data byte, the general call interrupt status bit sets on any general call.
The user must take corrective action by reprogramming the device address.
Set this bit to allow the slave ACK I
Clear this bit to disable recognition of general call commands.
I
Set to 1 to enable 10-bit address mode.
Clear to 0 to enable normal address mode.
I
Set by the user to enable I
Clear this bit to disable I
2
2
2
2
2
2
C early transmit interrupt enable bit.
C general call status and ID clear bit.
C hardware general call enable.
C general call enable.
C 10-bit address mode.
C slave enable bit.
Description
Reserved.
This bit is set to 1 if a start condition followed by a matching address is detected, a start byte (0x01) is
received, or general calls are enabled and a general call code of (0x00) is received.
This bit is cleared on receiving a stop condition.
This bit is set to 1 if a repeated start condition is detected.
This bit is cleared on receiving a stop condition.
2
C status register in slave mode.
2
C slave mode.
2
2
C slave mode.
C system. If it receives a 0x04 (write programmable part of the slave address by
2
C interface resets as per the I
Rev. B | Page 75 of 104
2
C general call commands.
2
C January 2000 bus specification. This command can
2
C general call, Address 0x00 (write). The device then
2
C January 2000 bus specification.
ADuC7124/ADuC7126