ADUC7126 Analog Devices, ADUC7126 Datasheet - Page 76

• Manufacturer Part Number: ADUC7126
• Description: Precision Analog Microcontroller, 12-Bit Analog I/O, Large Memory, ARM7TDMI MCU with Enhanced IRQ Handler
• Manufacturer: Analog Devices

Specifications of ADUC7126

• Mcu Core: ARM7 TDMI
• Mcu Speed (mips): 40
• Gpio Pins: 40
• Adc # Channels: 16
• Other: PWM

ADuC7124/ADuC7126
Bit
[12:11]
10
[9:8]
7
6
5
4
3
2
1
0
Name
I2CID[1:0]
I2CSS
I2CGCID[1:0]
I2CGC
I2CSBUSY
I2CSNA
I2CSRxFO
I2CSRXQ
I2CSTXQ
I2CSTFE
I2CETSTA
This bit is set to 1 when the slave Rx FIFO is not empty.
This bit causes an interrupt to occur when the I2CSRXENI bit in I2CxSCON is set.
The Rx FIFO must be read or flushed to clear this bit.
Description
I
[00] = received address matches I2CxID0.
[01] = received address matches I2CxID1.
[10] = received address matches I2CxID2.
[11] = received address matches I2CxID3.
I
This bit is set to 1 when a stop condition is detected after a previous start and matching address.
When the I2CSSENI bit in I2CxSCON is set, an interrupt is generated.
This bit is cleared by reading this register.
I
[00] = no general call received.
[01] = general call reset and program address.
[10] = general program address.
[11] = general call matching alternative ID.
Note that these bits are not cleared by a general call reset command.
Clear these bits by writing a 1 to the I2CGCCLR bit in I2CxSCON.
I
This bit is set to 1 if the slave receives a general call command of any type.
If the command received is a reset command, then all registers return to their default states.
If the command received is a hardware general call, the Rx FIFO holds the second byte of the command
and this can be compared with the I2CxALT register.
Clear this bit by writing a 1 to the I2CGCCLR bit in I2CxSCON.
I
Set to 1 when the slave receives a start condition.
Cleared by hardware if the received address does not match any of the I2CxIDx registers, the slave device
receives a stop condition, or a repeated start address does not match any of the I2CxIDx registers.
I
This bit is set to 1 when the slave responds to a bus address with a NACK. This bit is asserted if a NACK was
returned because there was no data in the Tx FIFO or the I2CNACKEN bit was set in the I2CxSCON register.
This bit is cleared in all other conditions.
Slave Rx FIFO overflow.
This bit is set to 1 when a byte is written to the Rx FIFO when it is already full.
This bit is cleared in all other conditions.
I
I
This bit is set to 1 when the slave receives a matching address followed by a read.
If the I2CSETEN bit in I2CxSCON = 0, this bit goes high just after the negative edge of SCL during the read
bit transmission.
If the I2CSETEN bit in I2CxSCON = 1, this bit goes high just after the positive edge of SCL during the read
bit transmission.
This bit causes an interrupt to occur when the I2CSTXENI bit in I2CxSCON is set.
This bit is cleared in all other conditions.
I
This bit goes high if the Tx FIFO is empty when a master requests data from the slave. This bit is asserted at
the rising edge of SCL during the read bit.
This bit is cleared in all other conditions.
I
If the I2CSETEN bit in I2CxSCON = 0, this bit goes high if the slave Tx FIFO is empty.
If the I2CSETEN bit in I2CxSCON = 1, this bit goes high just after the positive edge of SCL during the write
bit transmission.
This bit asserts once only for a transfer.
This bit is cleared after being read.
2
2
2
2
2
2
2
2
2
2
C address matching register. These bits indicate which I2CxIDx register matches the received address.
C stop condition after start detected bit.
C general call ID bits.
C general call status bit.
C slave busy status bit.
C slave NACK data bit.
C slave receive request bit.
C slave transmit request bit.
C slave FIFO underflow status bit.
C slave early transmit FIFO status bit.
Rev. B | Page 76 of 104