ADUC7126 Analog Devices, ADUC7126 Datasheet - Page 95

• Manufacturer Part Number: ADUC7126
• Description: Precision Analog Microcontroller, 12-Bit Analog I/O, Large Memory, ARM7TDMI MCU with Enhanced IRQ Handler
• Manufacturer: Analog Devices

Specifications of ADUC7126

• Mcu Core: ARM7 TDMI
• Mcu Speed (mips): 40
• Gpio Pins: 40
• Adc # Channels: 16
• Other: PWM

Timer3 (Watchdog Time)
Timer3 has two modes of operation: normal mode and
watchdog mode. The watchdog timer is used to recover from
an illegal software state. Once enabled, it requires periodic
servicing to prevent it from forcing a processor reset.
Normal Mode
Timer3 in normal mode is identical to Timer0, except for the
clock source and the count-up functionality. The clock source is
32 kHz from the PLL and can be scaled by a factor of 1, 16, or
256 (see Figure 55).
Watchdog Mode
Watchdog mode is entered by setting Bit 5 in the T3CON MMR.
Timer3 decreases from the value present in the T3LD register
until 0 is reached. T3LD is used as the timeout. The maximum
timeout can be 512 sec using the prescaler/256 and full scale in
T3LD. Timer3 is clocked by the internal 32 kHz crystal when
operating in the watchdog mode. Note that, to enter watchdog
mode successfully, Bit 5 in the T3CON MMR must be set after
writing to the T3LD MMR.
If the timer reaches 0, a reset or an interrupt occurs, depending
on Bit 1 in the T3CON register. To avoid reset or interrupt, any
value must be written to T3CLRI before the expiration period.
This reloads the counter with T3LD and begins a new timeout
period.
When watchdog mode is entered, T3LD and T3CON are write-
protected. These two registers cannot be modified until a reset
clears the watchdog enable bit, which causes Timer3 to exit
watchdog mode.
The Timer3 interface consists of four MMRs: T3LD, T3VAL,
T3CON, and T3CLRI.
T3LD Register
Name:
Address:
Default Value:
Access:
T3LD is a 16-bit load register.
32.768kHz
Figure 55. Timer3 Block Diagram
÷ 1, 16 OR 256
T3LD
0xFFFF0360
0x0000
Read/write
PRESCALER
COUNTER
UP/DOWN
TIMER3
VALUE
16-BIT
16-BIT
LOAD
WATCHDOG
RESET
TIMER3 IRQ
Rev. B | Page 95 of 104
T3VAL Register
Name:
Address:
Default Value:
Access:
T3VAL is a 16-bit read-only register that represents the current
state of the counter.
T3CON Register
Name:
Address:
Default Value:
Access:
T3CON is the configuration MMR described in Table 144.
Table 144. T3CON MMR Bit Descriptions
Bit
[31:9]
8
7
6
5
4
[3:2]
1
0
Value
00
01
10
11
T3VAL
0xFFFF0364
0xFFFF
Read only
T3CON
0xFFFF0368
0x0000
Read/write
Description
Reserved.
Count up.
Set by the user for Timer3 to count up.
Cleared by the user for Timer3 to count down
by default.
Timer3 enable bit.
Set by the user to enable Timer3.
Cleared by the user to disable Timer3 by
default.
Timer3 mode.
Set by the user to operate in periodic mode.
Cleared by the user to operate in free-running
mode (default mode).
Watchdog mode enable bit.
Set by the user to enable watchdog mode.
Cleared by the user to disable watchdog
mode by default.
Secure clear bit.
Set by the user to use the secure clear option.
Cleared by the user to disable the secure clear
option by default.
Prescale.
Source clock/1 by default.
Source clock/16.
Source clock/256.
Undefined. Equivalent to 00.
Watchdog IRQ option bit.
Set by the user to produce an IRQ instead of a
reset when the watchdog reaches 0.
Cleared by the user to disable the IRQ option.
Reserved.
ADuC7124/ADuC7126