ADUC7124 Analog Devices, ADUC7124 Datasheet - Page 14

• Manufacturer Part Number: ADUC7124
• Description: Precision Analog Microcontroller, 12-Bit Analog I/O, Large Memory, ARM7TDMI MCU with Enhanced IRQ Handler
• Manufacturer: Analog Devices

Specifications of ADUC7124

• Mcu Core: ARM7 TDMI
• Mcu Speed (mips): 40
• Sram (bytes): 32000Bytes
• Gpio Pins: 30
• Adc # Channels: 12

ADuC7124/ADuC7126
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Table 9. Pin Function Descriptions (ADuC7124 64-Lead LFCSP)
Pin No.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
Mnemonic
Exposed Paddle
ADC4
ADC5
ADC6
ADC7
ADC8
ADC9
ADCNEG
DACGND
DACV
DAC0/ADC12
DAC1/ADC13
TMS
TDI
DD
NOTES
1. THE EXPOSED PADDLE MUST BE SOLDERED TO THE PCB TO ENSURE PROPER
BM/P0.0/CMP
HEAT DISSIPATION, NOISE, AND MECHANICAL STRENGTH BENEFITS.
DAC0/ADC12
DAC1/ADC13
NC = NO CONNECT
OUT
ADCNEG
DACGND
DACV
/PLAI[7]
XCLKO
XCLKI
ADC4
ADC5
ADC6
ADC7
ADC8
ADC9
TMS
TDI
DD
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
PIN 1
INDICATOR
Description
Exposed Paddle. The LFCSP_VQ has an exposed paddle that must be left unconnected.
Single-Ended or Differential Analog Input 4.
Single-Ended or Differential Analog Input 5.
Single-Ended or Differential Analog Input 6.
Single-Ended or Differential Analog Input 7.
Single-Ended or Differential Analog Input 8.
Single-Ended or Differential Analog Input 9.
Bias Point or Negative Analog Input of the ADC in Pseudo Differential Mode. Must be
connected to the ground of the signal to convert. This bias point must be between 0 V
and 1 V.
Ground for the DAC. Typically connected to AGND.
3.3 V Power Supply for the DACs. Must be connected to AV
DAC0 Voltage Output (DAC0).
Single-Ended or Differential Analog Input 12 (ADC12).
DAC1 Voltage Output (DAC1).
Single-Ended or Differential Analog Input 13 (ADC13).
JTAG Test Port Input, Test Mode Select. Debug and download access.
JTAG Test Port Input, Test Data In.
Figure 7. ADuC7124 Pin Configuration
ADuC7124
(Not to Scale)
TOP VIEW
Rev. B | Page 14 of 104
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45
44
43
42
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40
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37
36
35
34
33
P1.3/SPM3/CTS/I2C1SDA/PLAI[3]
P1.4/SPM4/RI/SPICLK/PLAI[4]/IRQ2
P1.5/SPM5/DCD/SPIMISO/PLAI[5]/IRQ3
P4.1/PLAO[9]/SOUT1
P4.0/PLAO[8]/SIN1
P1.6/SPM6/PLAI[6]
P1.7/SPM7/DTR/SPICS/PLAO[0]
P3.7/PWM
P3.6/PWM
IOV
IOGND
P0.7/ECLK/XCLK/SPM8/PLAO[4]/SIN0
P2.0/SPM9/PLAO[5]/CONV
IRQ1/P0.5/ADC
IRQ0/P0.4/PWM
RST
DD
SYNC
TRIP
/PLAI[14]
/PLAI[15]
BUSY
TRIP
/PLAO[1]
/PLAO[2]
START
/SOUT0
DD
.