ADUC7124 Analog Devices, ADUC7124 Datasheet - Page 38

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ADUC7124

Manufacturer Part Number
ADUC7124
Description
Precision Analog Microcontroller, 12-Bit Analog I/O, Large Memory, ARM7TDMI MCU with Enhanced IRQ Handler
Manufacturer
Analog Devices
Datasheet

Specifications of ADUC7124

Mcu Core
ARM7 TDMI
Mcu Speed (mips)
40
Sram (bytes)
32000Bytes
Gpio Pins
30
Adc # Channels
12

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ADuC7124/ADuC7126
TYPICAL OPERATION
Once configured via the ADC control and channel selection
registers, the ADC converts the analog input and provides a
12-bit result in the ADC data register.
The top four bits are the sign bits. The 12-bit result is placed in
Bit 16 to Bit 27 as shown in Figure 30. Again, it should be noted
that in fully differential mode, the result is represented in twos
complement format. In pseudo differential and single-ended
modes, the result is represented in straight binary format.
The same format is used in DACxDAT, simplifying the software.
Current Consumption
The ADC in standby mode, that is, powered up but not
converting, typically consumes 640 µA. The internal reference
adds 140 µA. During conversion, the extra current is 0.3 µA
multiplied by the sampling frequency (in kHz).
Timing
Figure 31 gives details of the ADC timing. The user controls the
ADC clock speed and the number of acquisition clocks in the
ADCCON MMR. By default, the acquisition time is eight
clocks, and the clock divider is two. The number of extra clocks
(such as bit trial or write) is set to 19, which gives a sampling
rate of 774 kSPS. For conversion on temperature sensor, the
ADC acquisition time is automatically set to 16 clocks, and the
ADC clock divider is set to 32. When using multiple channels
including the temperature sensor, the timing settings revert to
the user-defined settings after reading the temperature sensor
channel.
ADC CLOCK
CONV
31
SIGN BITS
ADC
ADCDAT
START
BUSY
27
Figure 30. ADC Result Format
Figure 31. ADC Timing
ACQ
12-BIT ADC RESULT
BIT TRIAL
ADCSTA = 0
WRITE
ADC INTERRUPT
DATA
16 15
ADCSTA = 1
Rev. B | Page 38 of 104
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MMRS INTERFACE
The ADC is controlled and configured via the eight MMRs.
ADCCON Register
Name:
Address:
Default Value:
Access:
ADCCON is an ADC control register that allows the program-
mer to enable the ADC peripheral, select the mode of operation
of the ADC (either in single-ended mode, pseudo differential
mode, or fully differential mode), and select the conversion
type. This MMR is described in Table 30.
Table 30. ADCCON MMR Bit Descriptions
Bit
[15:14]
13
[12:10]
[9:8]
7
6
5
[4:3]
Value
000
001
010
011
100
101
00
01
10
11
00
01
10
11
Description
Reserved.
Set by the user to enable edge trigger mode.
Cleared by the user to enable level trigger
mode.
ADC clock speed.
f
1 MSPS ADC with an external clock <41.78 MHz.
f
f
f
f
f
ADC acquisition time.
Two clocks.
Four clocks.
Eight clocks (default value).
16 clocks.
Enable start conversion.
Set by the user to start any type of
conversion command.
Cleared by the user to disable a start
conversion (clearing this bit does not stop
the ADC when continuously converting).
Enable ADC
Set by the user to enable the ADC
Cleared by the user to disable the ADC
ADC power control.
Set by the user to place the ADC in normal
mode (the ADC must be powered up for at least
5 μs before it converts correctly).
Cleared by the user to place the ADC in power-
down mode.
Conversion mode.
Single-ended mode.
Differential mode.
Pseudo differential mode.
Reserved.
ADC
ADC
ADC
ADC
ADC
ADC
ADCCON
0xFFFF0500
0x0600
Read/write
/1. This divider is provided to obtain
/2 (default value).
/4.
/8.
/16.
/32.
BUSY
.
BUSY
BUSY
pin.
pin.

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