ADUC7124 Analog Devices, ADUC7124 Datasheet - Page 56

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ADUC7124

Manufacturer Part Number
ADUC7124
Description
Precision Analog Microcontroller, 12-Bit Analog I/O, Large Memory, ARM7TDMI MCU with Enhanced IRQ Handler
Manufacturer
Analog Devices
Datasheet

Specifications of ADUC7124

Mcu Core
ARM7 TDMI
Mcu Speed (mips)
40
Sram (bytes)
32000Bytes
Gpio Pins
30
Adc # Channels
12

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ADuC7124/ADuC7126
MMRs and Keys
The operating mode, clocking mode, and programmable clock
divider are controlled via three MMRs, PLLCON (see Table 73),
and POWCONx. PLLCON controls the operating mode of the
clock system, POWCON0 controls the core clock frequency and
the power-down mode, and POWCON1 controls the clock
frequency to I
Table 72. PLLKEYx Registers
Name
PLLKEY1
PLLKEY2
PLLCON Register
Name:
Address:
Default Value:
Access:
Table 73. PLLCON MMR Bit Descriptions
Bit
[7:6]
5
[4:2]
[1:0]
To prevent accidental programming, a certain sequence must be
followed to write to the PLLCON register.The PLLCON write
sequence is as follows:
1.
2.
3.
Table 74. POWKEYx Registers
Name
POWKEY1
POWKEY2
POWKEY1 and POWKEY2 are used to prevent accidental
programming to POWCON0.
Write Code 0xAA to Register PLLKEY1.
Write user value to Register PLLCON.
Write Code 0x55 to Register PLLKEY2.
Value
00
01
10
11
2
C and SPI.
Address
0xFFFF0410
0xFFFF0418
Name
OSEL
MDCLK
Address
0xFFFF0404
0xFFFF040C
Description
Reserved.
32 kHz PLL input selection.
Set by the user to select the internal
32 kHz oscillator. Set by default.
Cleared by the user to select the
external 32 kHz crystal.
Reserved.
Clocking modes.
Reserved.
PLL. Default configuration.
Reserved.
External clock on the P0.7 Pin.
Default Value
0x0000
0x0000
Default Value
0x0000
0x0000
PLLCON
0xFFFF0414
0x21
Read/write
Access
W
W
Access
W
W
Rev. B | Page 56 of 104
POWCON0 Register
Name:
Address:
Default Value:
Access:
Table 75. POWCON0 MMR Bit Descriptions
Bit
7
[6:4]
3
[2:0]
To prevent accidental programming, a certain sequence must be
followed to write to the POWCONx register. The POWCON0
write sequence is as follows:
1.
2.
3.
Table 76. POWKEYx Registers
Name
POWKEY3
POWKEY4
POWKEY3 and POWKEY4 are used to prevent accidental
programming to POWCON1.
POWCON1 Register
Name:
Address:
Default Value:
Access:
Write Code 0x01 to Register POWKEY1.
Write a user value to Register POWCON0.
Write Code 0xF4 to Register POWKEY2.
Value
000
001
010
011
100
Others
000
001
010
011
100
101
110
111
Address
0xFFFF0434
0xFFFF043C
Name
PC
CD
Description
Reserved.
Operating modes.
Active mode.
Pause mode.
Nap mode.
Sleep mode. IRQ0 to IRQ3 and Timer2
can wake up the part.
Stop mode. IRQ0 to IRQ3 can wake
up the part.
Reserved.
Reserved.
CPU clock divider bits.
41.78 MHz.
20.89 MHz.
10.44 MHz.
5.22 MHz.
2.61 MHz.
1.31 MHz.
653 kHz.
326 kHz.
POWCON0
0xFFFF0408
0x0003
Read/write
POWCON1
0xFFFF0438
0x124
Read/write
Default Value
0x0000
0x0000
Access
W
W

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