ADUC7124 Analog Devices, ADUC7124 Datasheet - Page 81

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ADUC7124

Manufacturer Part Number
ADUC7124
Description
Precision Analog Microcontroller, 12-Bit Analog I/O, Large Memory, ARM7TDMI MCU with Enhanced IRQ Handler
Manufacturer
Analog Devices
Datasheet

Specifications of ADUC7124

Mcu Core
ARM7 TDMI
Mcu Speed (mips)
40
Sram (bytes)
32000Bytes
Gpio Pins
30
Adc # Channels
12

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PROGRAMMABLE LOGIC ARRAY (PLA)
Every ADuC7124/ADuC7126 integrates a fully programmable
logic array (PLA) that consists of two independent but
interconnected PLA blocks. Each block consists of eight PLA
elements, giving each part a total of 16 PLA elements.
Each PLA element contains a two-input look up table that can
be configured to generate any logic output function based on
two inputs and a flip-flop. This is represented in Figure 51.
In total, 40 GPIO pins are available on the ADuC7124/ADuC7126
for the PLA. These include 16 input pins and 16 output pins that
must be configured in the GPxCON register as PLA pins before
using the PLA. Note that the comparator output is also included
as one of the 16 input pins.
The PLA is configured via a set of user MMRs. The output(s) of
the PLA can be routed to the internal interrupt system, to the
CONV
PLA output pins.
The two blocks can be interconnected as follows:
Table 117. Element Input/Output
Element
0
1
2
3
4
5
6
7
1
Not all pins in this table are connected to external pins. However, they may
be routed internally via the PLA. See Table 122 for further details.
Output of Element 15 (Block 1) can be fed back to Input 0 of
Mux 0 of Element 0 (Block 0).
Output of Element 7 (Block 0) can be fed back to Input 0 of
Mux 0 of Element 8 (Block 1).
START
PLA Block 0
Input
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P0.0
signal of the ADC, to an MMR, or to any of the 16
0
1
2
3
Figure 51. PLA Element
Output
P1.7
P0.4
P0.5
P0.6
P0.7
P2.0
P2.1
P2.2
A
B
LOOK-UP
TABLE
Element
8
9
10
11
12
13
14
15
1
PLA Block 1
Input
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
4
Output
P4.0
P4.1
P4.2
P4.3
P4.4
P4.5
P4.6
P4.7
Rev. B | Page 81 of 104
PLA MMRs Interface
The PLA peripheral interface consists of the 22 MMRs.
Table 118. PLAELMx Registers
Name
PLAELM0
PLAELM1
PLAELM2
PLAELM3
PLAELM4
PLAELM5
PLAELM6
PLAELM7
PLAELM8
PLAELM9
PLAELM10
PLAELM11
PLAELM12
PLAELM13
PLAELM14
PLAELM15
The PLAELMx are Element 0 to Element 15 control registers.
They configure the input and output mux of each element,
select the function in the look up table, and bypass/use the flip-
flop (see Table 119 and Table 122).
Table 119. PLAELMx MMR Bit Descriptions
Bit
[31:11]
[10:9]
[8:7]
6
5
[4:1]
0
Value
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Address
0xFFFF0B00
0xFFFF0B04
0xFFFF0B08
0xFFFF0B0C
0xFFFF0B10
0xFFFF0B14
0xFFFF0B18
0xFFFF0B1C
0xFFFF0B20
0xFFFF0B24
0xFFFF0B28
0xFFFF0B2C
0xFFFF0B30
0xFFFF0B34
0xFFFF0B38
0xFFFF0B3C
Description
Reserved.
Mux 0 control (see Table 122).
Mux 1 control (see Table 122).
Mux 2 control.
Set by the user to select the output of Mux 0. Cleared
by the user to select the bit value from PLADIN.
Mux 3 control.
Set by the user to select the input pin of the particular
element.
Cleared by the user to select the output of Mux 1.
Look-up table control.
0.
NOR.
B AND NOT A.
NOT A.
A AND NOT B.
NOT B.
EXOR.
NAND.
AND.
EXNOR.
B.
NOT A OR B.
A.
A OR NOT B.
OR.
1.
Mux 4 control.
Set by the user to bypass the flip-flop.
Cleared by the user to select the flip-flop (cleared by
default).
ADuC7124/ADuC7126
Default Value
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

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