ADUC7124 Analog Devices, ADUC7124 Datasheet - Page 87

• Manufacturer Part Number: ADUC7124
• Description: Precision Analog Microcontroller, 12-Bit Analog I/O, Large Memory, ARM7TDMI MCU with Enhanced IRQ Handler
• Manufacturer: Analog Devices

Specifications of ADUC7124

• Mcu Core: ARM7 TDMI
• Mcu Speed (mips): 40
• Sram (bytes): 32000Bytes
• Gpio Pins: 30
• Adc # Channels: 12

IRQVEC Register
The IRQ interrupt vector register, IRQVEC points to a memory
address containing a pointer to the interrupt service routine of
the currently active IRQ. This register should only be read when
an IRQ occurs and IRQ interrupt nesting has been enabled by
setting Bit 0 of the IRQCONN register.
Name:
Address:
Default Value:
Access:
Table 129. IRQVEC MMR Bit Descriptions
Bit
[31:23]
[22:7]
[6:2]
[1:0]
Priority Registers
The IRQ interrupt vector register, IRQVEC points to a memory
address containing a pointer to the interrupt service routine of
the currently active IRQ. This register should only be read when
an IRQ occurs and IRQ interrupt nesting has been enabled by
setting Bit 0 of the IRQCONN register.
IRQP0 Register
Name:
Address:
Default Value:
Access:
Table 130. IRQP0 MMR Bit Descriptions
Bit
31
[30:28]
27
[26:24]
23
[22:20]
19
Name
Flash1PI
Flash0PI
T3PI
Type
R
R/W
R
Reser
ved
IRQVEC
0xFFFF001C
0x00000000
Read only
IRQP0
0xFFFF0020
0x00000000
Read/write
Initial
Value
0
0
0
0
Description
Reserved.
A priority level of 0 to 7 can be set for the
Flash Block 1 controller interrupt source.
Reserved.
A priority level of 0 to 7 can be set for the
Flash Block 0 controller interrupt source.
Reserved.
A priority level of 0 to 7 can be set for
Timer 3.
Reserved.
Description
Always read as 0.
IRQBASE register value.
Highest priority source. This is a
value between 0 and 27 represent-
ing the possible interrupt sources.
For example, if the highest currently
active IRQ is Timer 2, then these bits
are [00100].
Reserved bits.
Rev. B | Page 87 of 104
Bit
[18:16]
15
[14:12]
11
[10:8]
7
[6:4]
[3:0]
IRQP1 Register
Name:
Address:
Default Value:
Access:
Table 131. IRQP1 MMR Bit Descriptions
Bit
31
[30:28]
27
[26:24]
23
[22:20]
19
[18:16]
15
[14:12]
11
[10:8]
7
[6:4]
5
[2:0]
Name
T2PI
T1PI
T0PI
SWINTP
Name
I2C1SPI
I2C1MPI
I2C0SPI
I2C0MPI
PLLPI
UART1PI
UART0PI
ADCPI
IRQP1
0xFFFF0024
0x00000000
Read/write
Description
Reserved.
A priority level of 0 to 7 can be set for the
I2C1 slave.
Reserved.
A priority level of 0 to 7 can be set for the
I2C1 master.
Reserved.
A priority level of 0 to 7 can be set for the
I2C0 slave.
Reserved.
A priority level of 0 to 7 can be set for the
I
Reserved.
A priority level of 0 to 7 can be set for the
PLL lock interrupt.
Reserved.
A priority level of 0 to 7 can be set for
UART1.
Reserved.
A priority level of 0 to 7 can be set for
UART0.
Reserved.
A priority level of 0 to 7 can be set for the
ADC interrupt source.
2
C 0 master.
Description
A priority level of 0 to 7 can be set for
Timer2.
Reserved.
A priority level of 0 to 7 can be set for
Timer1.
Reserved.
A priority level of 0 to 7 can be set for
Timer0.
Reserved.
A priority level of 0 to 7 can be set for the
software interrupt source.
Interrupt 0 cannot be prioritized.
ADuC7124/ADuC7126