ADUC7124 Analog Devices, ADUC7124 Datasheet - Page 88

• Manufacturer Part Number: ADUC7124
• Description: Precision Analog Microcontroller, 12-Bit Analog I/O, Large Memory, ARM7TDMI MCU with Enhanced IRQ Handler
• Manufacturer: Analog Devices

Specifications of ADUC7124

• Mcu Core: ARM7 TDMI
• Mcu Speed (mips): 40
• Sram (bytes): 32000Bytes
• Gpio Pins: 30
• Adc # Channels: 12

ADuC7124/ADuC7126
IRQP2 Register
Name:
Address:
Default Value:
Access:
Table 132. IRQP2 MMR Bit Descriptions
Bit
31
[30:28]
27
[26:24]
23
[22:20]
19
[18:16]
15
[14:12]
11
[10:8]
7
[6:4]
3
[2:0]
IRQP3 Register
Name:
Address:
Default Value:
Access:
Table 133. IRQP3 MMR Bit Descriptions
Bit
[31:7]
[6:4]
3
[2:0]
IRQCONN Register
The IRQCONN register is the IRQ and FIQ control register. It
contains two active bits: the first to enable nesting and prioritiza-
tion of IRQ interrupts and the other to enable nesting and
prioritization of FIQ interrupts.
If these bits are cleared, FIQs and IRQs can still be used, but it is
not possible to nest IRQs or FIQs, nor is it possible to set an
Name
PWMPI
PLA1PI
Name
IRQ3PI
IRQ2PI
PLA0PI
IRQ1PI
PSMPI
COMPI
IRQ0PI
SPIPI
IRQP2
0xFFFF0028
0x00000000
Read/write
IRQP3
0xFFFF002C
0x00000000
Read/write
Description
Reserved.
A priority level of 0 to 7 can be set for PWM.
Reserved.
A priority level of 0 to 7 can be set for PLA
IRQ1.
Description
Reserved.
A priority level of 0 to 7 can be set for IRQ3.
Reserved.
A priority level of 0 to 7 can be set for IRQ2.
Reserved.
A priority level of 0 to 7 can be set for PLA
IRQ0.
Reserved.
A priority level of 0 to 7 can be set for IRQ1.
Reserved.
A priority level of 0 to 7 can be set for the
power supply monitor interrupt source.
Reserved.
A priority level of 0 to 7 can be set for the
comparator.
Reserved.
A priority level of 0 to 7 can be set for IRQ0.
Reserved.
A priority level of 0 to 7 can be set for SPI.
Rev. B | Page 88 of 104
interrupt source priority level. In this default state, an FIQ does
have a higher priority than an IRQ.
Name:
Address:
Default Value:
Access:
Table 134. IRQCONN MMR Bit Descriptions
Bit
31:2
1
0
IRQSTAN Register
If IRQCONN Bit 0 is asserted and IRQVEC is read, one of the
IRQSTAN[7:0] bits is asserted. The bit that asserts depends on
the priority of the IRQ. If the IRQ is of Priority 0, then Bit 0
asserts, if Priority 1, then Bit 1 asserts, and so on. When a bit is
set in this register, all interrupts of that priority and lower are
blocked.
To clear a bit in this register, all bits of a higher priority must be
cleared first. It is only possible to clear one bit at a time. For
example, if this register is set to 0x09, writing 0xFF changes the
register to 0x08, and writing 0xFF a second time changes the
register to 0x00.
Name:
Address:
Default Value:
Access:
Table 135. IRQSTAN MMR Bit Descriptions
Bit
31:8
7:0
Name
ENFIQN
ENIRQN
Name
IRQCONN
0xFFFF0030
0x00000000
Read/write
IRQSTAN
0xFFFF003C
0x00000000
Read/write
Description
Reserved. These bits are reserved and should
not be written to.
Setting this bit to 1 enables nesting of FIQ
interrupts. Clearing this bit means no nesting
or prioritization of FIQs is allowed.
Setting this bit to 1 enables nesting of IRQ
interrupts. Clearing this bit means no nesting
or prioritization of IRQs is allowed.
Description
Reserved. These bits are reserved and should
not be written to.
Setting these bits to 1 enables nesting of FIQ
interrupts. Clearing these bits means no
nesting or prioritization of FIQs is allowed.