ADUC7122 Analog Devices, ADUC7122 Datasheet - Page 15

• Manufacturer Part Number: ADUC7122
• Description: Precision Analog Microcontroller, 12-Bit Analog I/O, ARM7TDMI® MCU
• Manufacturer: Analog Devices

Specifications of ADUC7122

• Mcu Core: ARM7 TDMI
• Mcu Speed (mips): 40
• Sram (bytes): 8192Bytes
• Gpio Pins: 32
• Adc # Channels: 13

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 9. Pin Function Descriptions
Pin No.
C12
D11
E11
C3
D3
E3
F3
G3
G10
C2
D2
Mnemonic
RST
P0.0/SCL1/PLAI[5]
P0.1/SDA1/PLAI[4]
P0.2/SPICLK/ADC
P0.3/SPIMISO/PLAO[12]/SYNC
P0.4/SPIMOSI/PLAI[11]/TRIP
P0.5/SPICS/PLAI[10]/CONVST
P0.6/MRST/PLAI[2]
P0.7/TRST/PLAI[3]
P1.0/SIN/SCL2/PLAI[7]
P1.1/SOUT/SDA2/PLAI[6]
Busy
/PLAO[13]
Type
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
M
A
B
C
D
G
H
K
E
F
L
J
1
1
1
Description
Reset Input (Active Low).
General-Purpose Input and Output Port 0.0 (P0.0).
I
Input to PLA Element 5 (PLAI[5]).
General-Purpose Input and Output Port 0.1 (P0.1).
I
Input to PLA Element 4 (PLAI[4]).
General-Purpose Input and Output Port 0.2 (P0.2).
SPI Clock (SPICLK).
Status of the ADC (ADC
Output of PLA Element 13 (PLAO[13]).
General-Purpose Input and Output Port 0.3 (P0.3).
SPI Master Input, Slave Output (SPIMISO).
Output of PLA Element 12 (PLAO[12]).
Input to Synchronously Reset PWM Counters Using an External Source (SYNC).
General-Purpose Input and Output Port 0.4 (P0.4).
SPI Master Out, Slave Input (SPIMOSI).
Input to PLA Element 11 (PLAI[11]).
Input that Allows the PWM Trip Interrupt to Be Triggered (TRIP).
General-Purpose Input and Output Port 0.5 (P0.5).
SPI Slave Select Input (SPICS).
Input to PLA Element 10 (PLAI[10]).
Initiates ADC Conversions Using PLA or Timer Output (CONVST).
General-Purpose Input and Output Port 0.6 (P0.6).
Power-On Reset Output (MRST).
Input to PLA Element 2 (PLAI[2])
General-Purpose Input and Output Port 0.7 (P0.7).
JTAG Test Port Input, Test Reset (TRST). Debug and download access.
Input to PLA Element 3 (PLAI[3]).
General-Purpose Input and Output Port 1.0 (P1.0).
Serial Input, Receive Data (RxD), UART (SIN)
I
Input to PLA Element 7 (PLAI[7]).
General-Purpose Input and Output Port 1.1 (P1.1).
Serial Output, Transmit Data (TxD), UART (SOUT)
I
Input to PLA Element 6 (PLAI[6]).
2
2
2
2
2
2
C Interface SCLOCK for I2C0 (SCL1).
C Interface SDATA for I2C0 (SDA1).
C Interface SCLOCK for I2C1 (SCL2).
C Interface SDATA for I2C1 (SDA2).
3
3
Figure 7. Pin Configuration
4
4
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5
ADuC7122
5
TOP VIEW
6
6
7
7
8
8
9 10 11 12
9 10 11 12
Busy
).
A
B
C
D
E
F
G
H
J
K
L
M
ADuC7122