ADUC7122 Analog Devices, ADUC7122 Datasheet - Page 16

• Manufacturer Part Number: ADUC7122
• Description: Precision Analog Microcontroller, 12-Bit Analog I/O, ARM7TDMI® MCU
• Manufacturer: Analog Devices

Specifications of ADUC7122

• Mcu Core: ARM7 TDMI
• Mcu Speed (mips): 40
• Sram (bytes): 8192Bytes
• Gpio Pins: 32
• Adc # Channels: 13

ADuC7122
Pin No.
H3
J3
B3
B2
F11
G11
H11
J11
H10
J10
C1
C9
C4
C11
D1
E1
E2
F2
D12
Mnemonic
P1.4/PWM1/PLAI[8]/ECLK/XCLK
P1.5/PWM2/PLAI[9]
P1.6/PLAO[5]
P1.7/PLAO[4]
P2.0/IRQ0/PLAI[13]
P2.1/IRQ1/PLAI[12]
P2.2/PLAI[1]
P2.3/IRQ2/PLAI[14]
P2.4/PWM5/PLAO[7]
P2.5/PWM6/PLAO[6]
P2.6/IRQ3/PLAI[15]
P2.7/PLAI[0]
P3.0/PLAO[0]
P3.1/PLAO[1]
P3.2/IRQ4/PWM3/PLAO[2]
P3.3/IRQ5/PWM4/PLAO[3]
P3.4/PLAO[8]
P3.5/PLAO[9]
P3.6/PLAO[10]
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
1
Description
General-Purpose Input and Output Port 1.4 (P1.4).
PWM1 Output (PWM1).
Input to PLA Element 8 (PLAI[8]).
Base System Clock Output (ECLK).
Base System Clock Input (XCLK).
General-Purpose Input and Output Port 1.5 (P1.5).
PWM2 Output (PWM2).
Input to PLA Element 9 (PLAI[9]).
General-Purpose Input and Output Port 1.6 (P1.6).
Output of PLA Element 5 (PLAO[5]).
General-Purpose Input and Output Port 1.7 (P1.7).
Output of PLA Element 4 (PLAO[4]).
General-Purpose Input and Output Port 2.0 (P2.0).
External Interrupt Request 0 (IRQ0).
Input to PLA Element 13 (PLAI[13]).
General-Purpose Input and Output Port 2.1 (P2.1).
External Interrupt Request 1 (IRQ1).
Input to PLA Element 12 (PLAI[12]).
General-Purpose Input and Output Port 2.2 (P2.2).
Input to PLA Element 1 (PLAI[1]).
General-Purpose Input and Output Port 2.3 (P2.3).
External Interrupt Request 2 (IRQ2).
Input to PLA Element 14 (PLAI[14]).
General-Purpose Input and Output Port 2.4 (P2.4).
PWM5 Output (PWM5).
Output of PLA Element 7 (PLAO[7]).
General-Purpose Input and Output Port 2.5 (P2.5).
PWM6 Output (PWM6).
Output of PLA Element 6 (PLAO[6]).
General-Purpose Input and Output Port 2.6 (P2.6).
External Interrupt Request 3 (IRQ3).
Input to PLA Element 15 (PLAI[15]).
General-Purpose Input and Output Port 2.7 (P2.7).
Input to PLA Element 0 (PLAI[0]).
General-Purpose Input and Output Port 3.0 (P3.0).
Output of PLA Element 0 (PLAO[0]).
General-Purpose Input and Output Port 3.1 (P3.1).
Output of PLA Element 1 (PLAO[1]).
General-Purpose Input and Output Port 3.2 (P3.2).
External Interrupt Request 4 (IRQ4).
PWM3 Output (PWM3).
Output of PLA Element 2 (PLAO[2]).
General-Purpose Input and Output Port 3.3 (P3.3).
External Interrupt Request 5 (IRQ5).
PWM4 Output (PWM4).
Output of PLA Element 3 (PLAO[3]).
General-Purpose Input and Output Port 3.4 (P3.4).
Output of PLA Element 8 (PLAO[8]).
General-Purpose Input and Output Port 3.5 (P3.5).
Output of PLA Element 9 (PLAO[9]).
General-Purpose Input and Output Port 3.6 (P3.6).
Output of PLA Element 10 (PLAO[10]).
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