ADUC7122 Analog Devices, ADUC7122 Datasheet - Page 45

• Manufacturer Part Number: ADUC7122
• Description: Precision Analog Microcontroller, 12-Bit Analog I/O, ARM7TDMI® MCU
• Manufacturer: Analog Devices

Specifications of ADUC7122

• Mcu Core: ARM7 TDMI
• Mcu Speed (mips): 40
• Sram (bytes): 8192Bytes
• Gpio Pins: 32
• Adc # Channels: 13

Using the DACs
The on-chip DAC architecture consists of a resistor string DAC
followed by an output buffer amplifier. The functional equivalent
is shown in Figure 29.
As illustrated in Figure 29, the reference source for each DAC is
user-selectable in software. It can be either AV
to-AV
to the voltage at the AVDD pin. In 0 V-to-V
output transfer function spans from 0 V to the internal 2.5 V
reference, V
The DAC output buffer amplifier features a true, rail-to-rail
output stage implementation. This means that when unloaded,
each output is capable of swinging to within less than 5 mV of
both AV
(when driving a 5 kΩ resistive load to ground) is guaranteed
through the full transfer function except Code 0 to Code 100,
and, in 0 V-to-AV
Linearity degradation near ground and AV
ration of the output amplifier, and a general representation of its
effects (neglecting offset and gain error) is illustrated in Figure 30.
The dotted line in Figure 30 indicates the ideal transfer function,
and the solid line represents what the transfer function may
look like with endpoint nonlinearities due to saturation of the
output amplifier. Note that Figure 30 represents a transfer function
in 0-to-AV
AV
portion of the transfer function follows the ideal line right to the
end (V
linearity errors.
DD
), the lower nonlinearity is similar. However, the upper
DD
REF
DD
mode, the DAC output transfer function spans from 0 V
in this case, not AV
and ground. Moreover, the DAC linearity specification
DD
REF
mode only. In 0 V-to-V
AV
V
.
REF
DD
DD
mode only, Code 3995 to Code 4095.
Figure 29. DAC Structure
R
R
R
R
R
DD
), showing no signs of endpoint
REF
mode (with V
REF
DD
DD
is caused by satu-
mode, the DAC
or V
DAC0
REF
REF
. In 0 V-
<
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The endpoint nonlinearities conceptually illustrated in
Figure 30 become worse as a function of output loading. The
ADuC7122 data sheet specifications assume a 5 kΩ resistive
load to ground at the DAC output. As the output is forced to
source or sink more current, the nonlinear regions at the top or
bottom (respectively) of Figure 30 become larger. With larger
current demands, this can significantly limit output voltage swing.
The DAC can be configured to retain its output voltage after a
watchdog or software reset by writing to the RSTCFG register.
LDO (LOW DROPOUT REGULATOR)
The ADuC7122 contains an integrated LDO that generates the
core supply voltage (LVDD) of approximately 2.6 V from the
IOVDD supply. Because the LDO is driven from IOVDD, the
IOVDD supply voltage needs to be greater than 2.7 V.
An external compensation capacitor (C
equivalent series resistance (ESR) must be placed very close to
the LVDD pin. This capacitor also acts as a storage of charge
and supplies an instantaneous charge required by the core,
particularly at the positive edge of the core clock (HCLK).
The LVDD voltage generated by the LDO is solely for providing
a supply for the ADuC7122. Therefore, users should not use the
LVDD pin as the power supply pin for any other chip. Also, the
IOVDD pin should have excellent power supply decoupling to
help improve line regulation performance of the LDO.
The LVDD pin has no reverse battery, current limit, or thermal
shutdown protection; therefore, it is essential that users of the
ADuC7122 do not short this pin to ground at anytime during
normal operation or during board manufacture.
Figure 30. Endpoint Nonlinearities Due to Amplifier Saturation
AV
DD
– 100mV
100mV
AV
DD
0x00000000
T
) of 0.47 μF with low
0x0FFF0000
ADuC7122