ADUC7122 Analog Devices, ADUC7122 Datasheet - Page 49

• Manufacturer Part Number: ADUC7122
• Description: Precision Analog Microcontroller, 12-Bit Analog I/O, ARM7TDMI® MCU
• Manufacturer: Analog Devices

Specifications of ADUC7122

• Mcu Core: ARM7 TDMI
• Mcu Speed (mips): 40
• Sram (bytes): 8192Bytes
• Gpio Pins: 32
• Adc # Channels: 13

DIGITAL PERIPHERALS
PWM GENERAL OVERVIEW
The ADuC7122 integrates a 6-channel PWM interface. The
PWM outputs can be configured to drive an H-bridge or can be
used as standard PWM outputs. On power-up, the PWM outputs
default to H-bridge mode. This ensures that the H-bridge
controlled motor is turned off by default. In standard PWM
mode, the outputs are arranged as three pairs of PWM pins.
Users have control over the period of each pair of outputs and
over the duty cycle of each individual output.
Table 77. PWM MMRs
Name
PWMCON1
PWM1COM1
PWM1COM2
PWM1COM3
PWM1LEN
PWM2COM1
PWM2COM2
PWM2COM3
PWM2LEN
PWM3COM1
PWM3COM2
PWM3COM3
PWM3LEN
PWMCON2
PWMICLR
In all modes, the PWMxCOMx MMRs control the point at
which the PWM outputs change state. An example of the first pair
of PWM outputs (PWM1 and PWM2) is shown in Figure 32.
Table 78. PWMCON1 MMR Bit Designations (Address = 0xFFFF0F80, Default Value = 0x0012)
Bit
15
14
13
12
11
10
9
Name
Reserved
SYNC
PWM6INV
PWM4NV
PWM2INV
PWMTRIP
ENA
Function
PWM control
Compare Register 1 for PWM Output 1 and Output 2
Compare Register 2 for PWM Output 1 and Output 2
Compare Register 3 for PWM Output 1 and Output 2
Frequency control for PWM Output 1 and Output 2
Compare Register 1 for PWM Output 3 and Output 4
Compare Register 2 for PWM Output 3 and Output 4
Compare Register 3 for PWM Output 3 and Output 4
Frequency control for PWM Output 3 and Output 4
Compare Register 1 for PWM Output 5 and Output 6
Compare Register 2 for PWM Output 5 and Output 6
Compare Register 3 for PWM Output 5 and Output 6
Frequency control for PWM Output 5 and Output 6
PWM convert start control
PWM interrupt clear
Enables PWM synchronization.
If HOFF = 0 and HMODE = 1.
Description
This bit is reserved.
Set to 1 by the user so that all PWM counters are reset on the next clock edge after the detection of a high-to-low
transition on the SYNC pin.
Cleared by the user to ignore transitions on the SYNC pin.
Set to 1 by the user to invert PWM6.
Cleared by the user to use PWM6 in normal mode.
Set to 1 by the user to invert PWM4.
Cleared by the user to use PWM4 in normal mode.
Set to 1 by the user to invert PWM2.
Cleared by the user to use PWM2 in normal mode.
Set to 1 by the user to enable PWM trip interrupt. When the PWMTRIP input is low, the PWMEN bit is cleared and an
interrupt is generated.
Cleared by the user to disable the PWMTRIP interrupt.
Set to 1 by the user to enable PWM outputs.
Cleared by the user to disable PWM outputs.
If HOFF = 1 and HMODE = 1, see Table 79.
If not in H-Bridge mode, this bit has no effect.
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The PWM clock is selectable via PWMCON1 with UCLK divided
by one of the following values: 2, 4, 8, 16, 32, 64, 128, or 256.
The length of a PWM period is defined by PWMxLEN.
The PWM waveforms are set by the count value of the 16-bit
timer and the compare registers contents, as shown in the
PWM1 and PWM2 waveforms in Figure 32.
The low-side waveform, PWM2, goes high when the timer
count reaches PWM1LEN, and it goes low when the timer
count reaches the value held in PWM1COM3 or when the
high-side waveform PWM1 goes low.
The high-side waveform, PWM1, goes high when the timer
count reaches the value held in PWM1COM1, and it goes low
when the timer count reaches the value held in PWM1COM2.
In H-bridge mode, HMODE = 1 and Table 78 determine the
PWM outputs.
HIGH SIDE
LOW SIDE
(PWM1)
(PWM2)
PWM1COM3
PWM1COM2
PWM1COM1
PWM1LEN
Figure 32. PWM Timing
ADuC7122