ADUC7122 Analog Devices, ADUC7122 Datasheet - Page 53

• Manufacturer Part Number: ADUC7122
• Description: Precision Analog Microcontroller, 12-Bit Analog I/O, ARM7TDMI® MCU
• Manufacturer: Analog Devices

Specifications of ADUC7122

• Mcu Core: ARM7 TDMI
• Mcu Speed (mips): 40
• Sram (bytes): 8192Bytes
• Gpio Pins: 32
• Adc # Channels: 13

Table 85. GPxPAR Register
Name
GP0PAR
GP1PAR
GP2PAR
GP3PAR
GPxPAR programs the parameters for Port 0, Port 1, Port 2, and
Port 3. Note that the GPxDAT MMR must always be written
after changing the GPxPAR MMR.
Table 86. GPxPAR MMR Bit Designations
Bit
31:29
28
27:25
24
23:21
20
19:17
16
15:13
12
11:9
8
7:5
4
3:1
0
Table 87. GPxDAT Register
Name
GP0DAT
GP1DAT
GP2DAT
GP3DAT
GPxDAT is a Port x configuration and data register. It configures
the direction of the GPIO pins of Port x, sets the output value
for the pins configured as outputs, and receives and stores the
input value of the pins configured as inputs.
Table 88. GPxDAT MMR Bit Designations
Bit
31:24
23:16
15:8
7:0
Table 89. GPxSET Register
Name
GP0SET
GP1SET
GP2SET
GP3SET
Description
Direction of the data.
Set to 1 by the user to configure the GPIO pin as an output.
Cleared to 0 by user to configure the GPIO pin as an input.
Port x data output.
Reflect the state of Port x pins at reset (read only).
Port x data input (read only).
Description
Reserved
Pull-up disable Px.7 pin
Reserved
Pull-up disable Px.6 pin
Reserved
Pull-up disable Px.5 pin
Reserved
Pull-up disable Px.4 pin
Reserved
Pull-up disable Px.3 pin
Reserved
Pull-up disable Px.2 pin
Reserved
Pull-up disable Px.1 pin
Reserved
Pull-up disable Px.0 pin
Address
0xFFFF0D20
0xFFFF0D30
0xFFFF0D40
0xFFFF0D50
Address
0xFFFF0D24
0xFFFF0D34
0xFFFF0D44
0xFFFF0D54
Address
0xFFFF0D2C
0xFFFF0D3C
0xFFFF0D4C
0xFFFF0D5C
Default Value
0x20000000
0x00000000
0x00000000
0x00222222
Default Value
0x000000XX
0x000000XX
0x000000XX
0x000000XX
Default Value
0x000000XX
0x000000XX
0x000000XX
0x000000XX
Access
R/W
R/W
R/W
R/W
Access
R/W
R/W
R/W
R/W
Access
W
W
W
W
Rev. 0 | Page 53 of 96
Table 90. GPxSET MMR Bit Designations
Bit
31: 24
23:16
15: 0
GPxSET is a data set Port x register.
Table 91. GPxCLR Register
Name
GP0CLR
GP1CLR
GP2CLR
GP3CLR
GPxCLR is a data clear Port x register.
Table 92. GPxCLR MMR Bit Designations
Bit
31:24
23:16
15:0
Open-collector functionality is available on the following GPIO
pins: P1.7, P1.6, P2.x, and P3.x. Open-collector functionality can be
configured using GP1OCE[7:6], GP2OCE[7:0], and GP3OCE[7:0].
Table 93. GPxOCE MMR Bit Designations
Bit
31:8
7
6
5
4
3
2
1
0
Description
Reserved.
Data Port x set bit.
Set to 1 by the user to set bit on Port x; also sets the
corresponding bit in the GPxDAT MMR.
Cleared to 0 by the user; does not affect the data output.
Reserved.
Description
Reserved.
Data Port x clear bit.
Set to 1 by the user to clear bit on Port x; also clears
the corresponding bit in the GPxDAT MMR.
Cleared to 0 by the user; does not affect the data
output.
Reserved.
Description
Reserved.
GPIO Px.7 open-collector enable
Set to 1 by the user to enable open-collector
Set to 0 by the user to disable open collector
GPIO Px.6 open-collector enable
Set to 1 by the user to enable open-collector
Set to 0 by the user to disable open-collector
GPIO Px.5 open-collector enable
Set to 1 by the user to enable open-collector
Set to 0 by the user to disable open-collector
GPIO Px.4 open-collector enable
Set to 1 by the user to enable open-collector
Set to 0 by the user to disable open-collector
GPIO Px.3 open-collector enable
Set to 1 by the user to enable open-collector
Set to 0 by the user to disable open-collector
GPIO Px.2 open-collector enable
Set to 1 by the user to enable open-collector
Set to 0 by the user to disable open-collector
GPIO Px.1 open-collector enable
Set to 1 by the user to enable open-collector
Set to 0 by the user to disable open-collector
GPIO Px.0 open-collector enable
Set to 1 by the user to enable open-collector
Set to 0 by the user to disable open-collector
Address
0xFFFF0D28
0xFFFF0D38
0xFFFF0D48
0xFFFF0D58
Default Value
0x000000XX
0x000000XX
0x000000XX
0x000000XX
ADuC7122
Access
W
W
W
W