ADUC7122 Analog Devices, ADUC7122 Datasheet - Page 71

• Manufacturer Part Number: ADUC7122
• Description: Precision Analog Microcontroller, 12-Bit Analog I/O, ARM7TDMI® MCU
• Manufacturer: Analog Devices

Specifications of ADUC7122

• Mcu Core: ARM7 TDMI
• Mcu Speed (mips): 40
• Sram (bytes): 8192Bytes
• Gpio Pins: 32
• Adc # Channels: 13

SPIRX Register
Name:
Address:
Default Value:
Access:
Function:
SPITX Register
Name:
Address:
Default Value:
Access:
Function:
Table 112. SPICON MMR Bit Designations
Bit
15:14
13
12
11
10
9
Name
SPIMDE
SPITFLH
SPIRFLH
SPICONT
SPILP
SPIOEN
SPIRX
0xFFFF0A04
0x00
Read
This 8-bit MMR is the SPI receive register.
SPITX
0xFFFF0A08
0x00
Write
This 8-bit MMR is the SPI transmit register.
Description
SPI IRQ mode bits. These bits configure when the Tx/Rx interrupts occur in a transfer.
00 = Tx interrupt occurs when one byte has been transferred. Rx interrupt occurs when one or more bytes have been
received by the FIFO.
01 = Tx interrupt occurs when two bytes have been transferred. Rx interrupt occurs when two or more bytes have been
received by the FIFO.
10 = Tx interrupt occurs when three bytes have been transferred. Rx interrupt occurs when three or more bytes have
been received by the FIFO.
11 = Tx interrupt occurs when four bytes have been transferred. Rx interrupt occurs when the Rx FIFO is full, or four
bytes present.
SPI Tx FIFO flush enable bit.
Set this bit to flush the Tx FIFO. This bit does not clear itself and should be toggled if a single flush is required. If this bit
is left high, then either the last transmitted value or 0x00 is transmitted depending on the SPIZEN bit. When the flush
enable bit is set, the FIFO is cleared within a single microprocessor cycle.
Any writes to the Tx FIFO are ignored while this bit is set.
Clear this bit to disable Tx FIFO flushing.
SPI Rx FIFO flush enable bit.
Set this bit to flush the Rx FIFO. This bit does not clear itself and should be toggled if a single flush is required. When the
flush enable bit is set, the FIFO is cleared within a single microprocessor cycle.
If this bit is set, all incoming data is ignored and no interrupts are generated.
If set and SPITMDE = 0, a read of the Rx FIFO initiates a transfer.
Clear this bit to disable Rx FIFO flushing.
Continuous transfer enable.
Set by the user to enable continuous transfer. In master mode, the transfer continues until no valid data is available in
the Tx register. SPICS is asserted and remains asserted for the duration of each 8-bit serial transfer until Tx is empty.
Cleared by the user to disable continuous transfer. Each transfer consists of a single 8-bit serial transfer. If valid data
exists in the SPITX register, then a new transfer is initiated after a stall period of one serial clock cycle.
Loop back enable bit.
Set by the user to connect MISO to MOSI and test software.
Cleared by the user to place in normal mode.
Slave MISO output enable bit.
Set this bit for SPIMISO to operate as normal.
Clear this bit to disable the output driver on the SPIMISO pin. The SPIMISO pin is open-drain when this bit is clear.
Rev. 0 | Page 71 of 96
SPIDIV Register
Name:
Address:
Default Value:
Access:
Function:
SPI Control Register
Name:
Address:
Default Value:
Access:
Function:
SPIDIV
0xFFFF0A0C
0x1B
Read/write
register.
SPICON
0xFFFF0A10
0x0000
Read/write
This 16-bit MMR configures the SPI
peripheral in both master and slave modes.
This 8-bit MMR is the SPI baud rate selection
ADuC7122