ADUC7122 Analog Devices, ADUC7122 Datasheet - Page 74

• Manufacturer Part Number: ADUC7122
• Description: Precision Analog Microcontroller, 12-Bit Analog I/O, ARM7TDMI® MCU
• Manufacturer: Analog Devices

Specifications of ADUC7122

• Mcu Core: ARM7 TDMI
• Mcu Speed (mips): 40
• Sram (bytes): 8192Bytes
• Gpio Pins: 32
• Adc # Channels: 13

ADuC7122
Table 115. PLAELMx MMR Bit Descriptions
Bit
31:11
10:9
8:7
6
5
4:1
0
Table 118. Feedback Configuration
Bit
10:9
8:7
Value
1
0
1
0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Value
00
01
10
11
00
01
10
11
Description
Reserved.
Mux 0 control (see Table 118).
Mux 1 control (see Table 118).
Mux 2 control.
Set by user to select the output of Mux 0.
Cleared by user to select the bit value from the
PLADIN register.
Mux 3 control.
Set by user to select the input pin of the
particular element.
Cleared by user to select the output of Mux 1.
Look-up table control.
0.
NOR.
B AND NOT A.
NOT A.
A AND NOT B.
NOT B.
EXOR.
NAND.
AND.
EXNOR.
B.
NOT A OR B.
A.
A OR NOT B.
OR.
1.
Mux 4 control. Set by user to bypass the flip-
flop. Cleared by user to select the flip-flop
(cleared by default).
PLAELM0
Element 15
Element 2
Element 4
Element 6
Element 1
Element 3
Element 5
Element 7
PLAELM1 to PLAELM7
Element 0
Element 2
Element 4
Element 6
Element 1
Element 3
Element 5
Element 7
Rev. 0 | Page 74 of 96
Table 116. PLACLK Register
Name
PLACLK
PLACLK is the clock selection for the flip-flops of Block 0 and
Block 1. Note that the maximum frequency when using the
GPIO pins as the clock input for the PLA blocks is 41.78 MHz.
Table 117. PLACLK MMR Bit Descriptions
Bit
7
6:4
3
2:0
PLAELM8
Element 7
Element 10
Element 12
Element 14
Element 9
Element 11
Element 13
Element 15
Value
000
001
010
011
100
101
Other
000
001
010
011
100
101
Other
Address
0xFFFF0B40
Description
Reserved.
Block 1 clock source selection.
GPIO clock on P0.5.
GPIO clock on P0.0.
GPIO clock on P0.7.
HCLK.
External crystal (OCLK) (32.768 kHz).
Timer1 overflow.
Reserved.
Reserved.
Block 0 clock source selection.
GPIO clock on P0.5.
GPIO clock on P0.0.
GPIO clock on P0.7.
HCLK.
External crystal (OCLK) (32.768 kHz).
Timer1 overflow.
Reserved.
PLAELM9 to PLAELM15
Element 8
Element 10
Element 12
Element 14
Element 9
Element 11
Element 13
Element 15
Default Value
0x00
Access
R/W