ADUC7122 Analog Devices, ADUC7122 Datasheet - Page 78

• Manufacturer Part Number: ADUC7122
• Description: Precision Analog Microcontroller, 12-Bit Analog I/O, ARM7TDMI® MCU
• Manufacturer: Analog Devices

Specifications of ADUC7122

• Mcu Core: ARM7 TDMI
• Mcu Speed (mips): 40
• Sram (bytes): 8192Bytes
• Gpio Pins: 32
• Adc # Channels: 13

ADuC7122
FIQEN
FIQEN provides the value of the current enable mask. When a
bit is set to 1, the corresponding source request is enabled
to create an FIQ exception. When a bit is set to 0, the corre-
sponding source request is disabled or masked, which does not
create an FIQ exception. The FIQEN register cannot be used to
disable an interrupt.
FIQEN Register
Name:
Address:
Default Value:
Access:
FIQCLR
FIQCLR is a write-only register that allows the FIQEN register
to clear to mask an interrupt source. Each bit that is set to 1
clears the corresponding bit in the FIQEN register without
affecting the remaining bits. The pair of registers, FIQEN and
FIQCLR, allows independent manipulation of the enable mask
without requiring an atomic read-modify-write.
FIQCLR Register
Name:
Address:
Default Value:
Access:
FIQSTA
FIQSTA is a read-only register that provides the current enabled
FIQ source status (effectively a logic AND of the FIQSIG and
FIQEN bits). When set to 1, that source generates an active FIQ
request to the ARM7TDMI core. There is no priority encoder
or interrupt vector generation. This function is implemented in
software in a common interrupt handler routine.
FIQSTA Register
Name:
Address:
Default Value:
Access:
Programmed Interrupts
Because the programmed interrupts are not maskable, they are
controlled by another register (SWICFG) that writes into both
IRQSTA and IRQSIG registers and/or the FIQSTA and FIQSIG
registers at the same time.
FIQEN
0xFFFF0108
0x00000000
Read/write
FIQSTA
0xFFFF0100
0x00000000
Read only
FIQCLR
0xFFFF010C
0x00000000
Write only
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The 32-bit register dedicated to software interrupt is SWICFG,
described in Table 129. This MMR allows the control of a
programmed source interrupt.
Table 129. SWICFG MMR Bit Designations
Bit
31 to 3
2
1
0
Any interrupt signal must be active for at least the minimum
interrupt latency time to be detected by the interrupt controller
and by the user in the IRQSTA/FIQSTA register.
Vectored Interrupt Controller (VIC)
The ADuC7122 incorporates an enhanced interrupt control
system or vectored interrupt controller. The vectored interrupt
controller for IRQ interrupt sources is enabled by setting Bit 0
of the IRQCONN register. Similarly, Bit 1 of IRQCONN enables
the vectored interrupt controller for the FIQ interrupt sources.
The vectored interrupt controller provides the following
enhancements to the standard IRQ/FIQ interrupts:



IRQ_SOURCE
FIQ_SOURCE
Vectored interrupts—allow a user to define separate
interrupt service routine addresses for every interrupt
source. This is achieved by using the IRQBASE and
IRQVEC registers.
IRQ/FIQ interrupts—can be nested up to eight levels
depending on the priority settings. An FIQ still has a
higher priority than an IRQ. Therefore, if the VIC is enabled
for both the FIQ and IRQ and prioritization is maximized,
then it is possible to have 16 separate interrupt levels.
Programmable interrupt priorities—using the IRQP0 to
IRQP2 registers, an interrupt source can be assigned an
interrupt priority level value between 1 and 8.
BIT 31 TO
UNUSED
Description
Reserved.
Programmed Interrupt FIQ. Setting/clearing this bit
corresponds to setting/clearing Bit 1 of FIQSTA and
FIQSIG.
Programmed Interrupt IRQ. Setting/clearing this bit
corresponds to setting/clearing Bit 1 of IRQSTA and
IRQSIG.
Reserved.
BIT 23
PER INTERRUPT (IRQP0/IRQP1/IRQP2)
PROGRAMMABLE PRIORITY
BIT 22 TO BIT 7
INTERRUPT VECTOR
(IRQBASE)
Figure 36. Interrupt Structure
INTERNAL
ARBITER
LOGIC
ACTIVE IRQ
PRIORITY
HIGHEST
BIT 6 TO
BIT 2
BIT 1 TO
BIT 0
LSB
POINTER TO
FUNCTION
(IRQVEC)