ADUC7023 Analog Devices, ADUC7023 Datasheet - Page 23

• Manufacturer Part Number: ADUC7023
• Description: Precision Analog Microcontroller, 12-Bit Analog I/O, ARM7TDMI MCU
• Manufacturer: Analog Devices

Specifications of ADUC7023

• Mcu Core: ARM7 TDMI
• Mcu Speed (mips): 40
• Sram (bytes): 8192Bytes
• Gpio Pins: 20
• Adc # Channels: 12
• Other: PWM

Table 10. IRQ Address Base = 0xFFFF0000
Address
0x0000
0x0004
0x0008
0x000C
0x0010
0x0014
0x001C
0x0020
0x0024
0x0028
0x002C
0x0030
0x0034
0x0038
0x003C
0x0100
0x0104
0x0108
0x010C
0x011C
0x013C
Table 11. System Control Address Base = 0xFFFF0200
Address
0x0220
0x0230
0x0234
0x0248
0x024C
0x0250
1
2
N/A means not applicable.
Updated by kernel.
Name
IRQSTA
IRQSIG
IRQEN
IRQCLR
SWICFG
IRQBASE
IRQVEC
IRQP0
IRQP1
IRQP2
RESERVED
IRQCONN
IRQCONE
IRQCLRE
IRQSTAN
FIQSTA
FIQSIG
FIQEN
FIQCLR
FIQVEC
FIQSTAN
Name
Remap
RSTSTA
RSTCLR
RSTKEY1
RSTCFG
RSTKEY2
2
Byte
1
1
1
1
1
1
Byte
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
R/W
W
R/W
W
Access Type
R/W
W
R
R
R/W
W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R/W
W
R
RW
Access Type
W
0x00
0xXX
0xXX
Default Value
0x01
0x00
0x00
Default Value
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
Rev. B | Page 23 of 96
1
Description
Remap control register.
RSTSTA status MMR.
RSTCLR MMR for clearing RSTSTA register.
0x76 should be written to this register before writing to RSTCFG.
This register allows the DAC and GPIO outputs to retain state after a
watchdog or software reset.
0xB1 should be written to this register after writing to RSTCFG.
Description
Active IRQ source.
Current state of all IRQ sources (enabled and disabled).
Enabled IRQ sources.
MMR to disable IRQ sources.
Software interrupt configuration MMR.
Base address of all vectors. Points to start of a 64-byte memory block
which can contain up to 32 pointers to separate subroutine handlers.
This register contains the subroutine address for the currently active IRQ
source.
This register contains the interrupt priority setting for Interrupt Source 1
to Interrupt Source 7. An interrupt can have a priority setting of 0 to 7.
This register contains the interrupt priority setting for Interrupt Source 8
to Interrupt Source 15.
This register contains the interrupt priority setting for Interrupt Source 16 to
Interrupt Source 21.
Reserved.
Used to enable IRQ and FIQ interrupt nesting.
This register configures the external interrupt sources as rising edge,
falling edge, or level triggered.
Used to clear an edge level triggered interrupt source.
This register indicates the priority level of an interrupt that has just
caused an interrupt exception.
Active FIQ source.
Current state of all FIQ sources (enabled and disabled).
Enabled FIQ sources.
MMR to disable FIQ sources.
FIQ interrupt vector.
This register indicates the priority level of an FIQ that has just caused an
FIQ exception.
ADuC7023