ADUC7023 Analog Devices, ADUC7023 Datasheet - Page 33

• Manufacturer Part Number: ADUC7023
• Description: Precision Analog Microcontroller, 12-Bit Analog I/O, ARM7TDMI MCU
• Manufacturer: Analog Devices

Specifications of ADUC7023

• Mcu Core: ARM7 TDMI
• Mcu Speed (mips): 40
• Sram (bytes): 8192Bytes
• Gpio Pins: 20
• Adc # Channels: 12
• Other: PWM

Single-Ended Mode
In single-ended mode, SW2 is always connected internally to
ground. The V
V
Analog Input Structure
Figure 27 shows the equivalent circuit of the analog input structure
of the ADC. The four diodes provide ESD protection for the analog
inputs. Care must be taken to ensure that the analog input signals
never exceed the supply rails by more than 300 mV; this causes
these diodes to become forward-biased and start conducting
into the substrate. These diodes can conduct up to 10 mA
without causing irreversible damage to the part.
The C1 capacitors in Figure 27 are typically 4 pF and can be
primarily attributed to pin capacitance. The resistors are
lumped components made up of the on resistance of the
switches. The value of these resistors is typically about 100 Ω.
The C2 capacitors are the ADC sampling capacitors and
typically have a capacitance of 16 pF.
For ac applications, removing high frequency components from
the analog input signal is recommended by using an RC low-
pass filter on the relevant analog input pins. In applications
where harmonic distortion and signal-to-noise ratio are critical,
the analog input should be driven from a low impedance
source. Large source impedances significantly affect the ac
performance of the ADC. This can necessitate the use of an
input buffer amplifier. The choice of the op amp is a function of
the particular application. Figure 28 and Figure 29 give an
example of an ADC front end.
AIN11
Figure 27. Equivalent Analog Input Circuit Conversion Phase: Switches Open,
AIN0
IN+
is 0 V to V
MUX
CHANNEL+
IN−
REF
Figure 26. ADC in Single-Ended Mode
C1
C1
pin can be floating. The input signal range on
.
CHANNEL–
Track Phase: Switches Closed
B
A
AV
AV
SW1
DD
DD
D
D
D
D
C
C
S
S
R1 C2
R1 C2
SW3
COMPARATOR
CAPACITIVE
CAPACITIVE
CONTROL
DAC
LOGIC
DAC
Rev. B | Page 33 of 96
When no amplifier is used to drive the analog input, limit the
source impedance to values lower than 1 kΩ. The maximum
source impedance depends on the amount of total harmonic
distortion (THD) that can be tolerated. The THD increases as
the source impedance increases and the performance degrades.
DRIVING THE ANALOG INPUTS
Internal or external references can be used for the ADC. When
operating in differential mode, there are restrictions on the
common-mode input signal (V
the reference value and supply voltage used to ensure that the
signal remains within the supply rails. Table 27 gives some
calculated V
Table 27. V
AV
3.3 V
3.0 V
CALIBRATION
By default, the factory-set values written to the ADC offset
(ADCOF) and gain coefficient registers (ADCGN) yield
optimum performance in terms of endpoint errors and linearity
for standalone operation of the part (see the Specifications
section). If system calibration is required, it is possible to
modify the default offset and gain coefficients to improve
endpoint errors, but note that any modification to the factory-
set ADCOF and ADCGN values can degrade ADC linearity
performance.
For system offset error correction, the ADC channel input stage
must be tied to AGND. A continuous software ADC conversion
loop must be implemented by modifying the value in ADCOF until
the ADC result (ADCDAT) reads Code 0 to Code 1. If the
ADCDAT value is greater than 1, ADCOF should be decremented
until ADCDAT reads Code 0 to Code 1. Offset error correction
is done digitally and has a resolution of 0.25 LSB and a range of
±3.125% of V
DD
Figure 28. Buffering Single-Ended/Pseudo Differential Input
V
2.5 V
2.048 V
1.25 V
2.5 V
2.048 V
1.25 V
REF
CM
V
CM
REF
REF
Ranges
minimum and V
Figure 29. Buffering Differential Inputs
.
V
1.25 V
1.024 V
0.75 V
1.25 V
1.024 V
0.75 V
CM
Min
10Ω
0.01µF
V
2.05 V
2.276 V
2.55 V
1.75 V
1.976 V
2.25 V
CM
CM
CM
), which is dependent upon
Max
maximum values.
ADuC7023
ADC0
ADuC7023
ADC0
ADC1
Signal Peak-to-Peak
2.5 V
2.048 V
1.25 V
2.5 V
2.048 V
1.25 V
ADuC7023