ADUC7023 Analog Devices, ADUC7023 Datasheet - Page 58

• Manufacturer Part Number: ADUC7023
• Description: Precision Analog Microcontroller, 12-Bit Analog I/O, ARM7TDMI MCU
• Manufacturer: Analog Devices

Specifications of ADUC7023

• Mcu Core: ARM7 TDMI
• Mcu Speed (mips): 40
• Sram (bytes): 8192Bytes
• Gpio Pins: 20
• Adc # Channels: 12
• Other: PWM

ADuC7023
I
The ADuC7023 incorporates two I
configured as a fully I
a fully I
The two pins used for data transfer, SDA and SCL, are configured
in a wire-AND format that allows arbitration in a multimaster
system. These pins require external pull-up resistors. Typical
pull-up values are between 4.7 kΩ and 10 kΩ.
The I
grammed by the user. This ID can be modified any time a
transfer is not in progress. The user can configure the interface
to respond to four slave addresses.
The transfer sequence of an I
device initiating a transfer by generating a start condition while
the bus is idle. The master transmits the slave device address
and the direction of the data transfer (read or/write) during the
initial address transfer. If the master does not lose arbitration
and the slave acknowledges the data, transfer is initiated. This
continues until the master issues a stop condition and the bus
becomes idle.
The I
at any given time. The same I
support master and slave modes.
The I
repeated start conditions. In master mode, the ADuC7023 can
be programmed to generate a repeated start. In slave mode, the
ADuC7023 recognizes repeated start conditions. In master and
slave mode, the part recognizes both 7-bit and 10-bit bus addresses.
In I
from a single slave up to 512 bytes in a single transfer sequence.
Clock stretching is supported in both master and slave modes.
In slave mode, the ADuC7023 can be programmed to return a
NACK. This allows the validiation of checksum bytes at the end
of I2C transfers. Bus arbitration in master mode is supported.
Internal and external loopback modes are supported for I
hardware testing. In loopback mode. The transmit and receive
circuits in both master and slave mode contain 2-byte FIFOs.
Status bits are available to the user to control these FIFOs.
CONFIGURING EXTERNAL PINS FOR I
FUNCTIONALITY
The I
and P0.6 and P0.7 for I
P0.4 and P0.6 are the I
I
SDA0), Bit 16 and Bit 20 of the GP0CON register must be set to
1 to enable I
(SCL1, SDA1), Bit 25 and Bit 29 of the GP0CON register must
be set to 1 to enable I
I
and avaliable at P1.6 and P1.7 on 40-lead pacakge.
2
2
2
C data signals. For instance, to configure I
C1 function is avaliable at P0.6 and P0.7 on 32-lead package
C
2
C master mode, the ADuC7023 supports continuous reads
2
2
2
2
C bus peripheral address in the I
C peripheral can only be configured as a master or slave
C interface on the ADuC7023 includes support for
C pins of the ADuC7023 device are P0.4 and P0.5 for I
2
C bus-compatible slave device.
2
C mode. On the other hand, to configure I
2
2
C mode, as shown in the GPIO section.
C-compatible I
2
C clock signals and P0.5 and P0.7 are the
2
C1.
2
2
C system consists of a master
C channel cannot simultaneously
2
C peripherals that may be
2
C bus master device or as
2
C bus system is pro-
2
C0 pins (SCL0,
2
C
2
C1 pins
2
C
Rev. B | Page 58 of 96
2
C0
SERIAL CLOCK GENERATION
The I
transfer. The master channel can be configured to operate in
fast mode (400 kHz) or standard mode (100 kHz).
The bit rate is defined in the I2CDIV MMR as follows:
where:
f
by POWCON1 Bit 4 to Bit 0.
DIVH is the high period of the clock.
DIVL is the low period of the clock.
Thus, for 100 kHz operation,
and for 400 kHz,
The I2CDIV register corresponds to DIVH:DIVL.
I
Slave Mode
In slave mode, the registers I2CxID0, I2CxID1, I2CxID2, and
I2CxID3 contain the device IDs. The device compares the four
I2CxIDx registers to the address byte received from the bus
master. To be correctly addressed, the 7 MSBs of either ID
register must be identical to that of the 7 MSBs of the first
received address byte. The LSB of the ID registers (the transfer
direction bit) is ignored in the process of address recognition.
The ADuC7023 also supports 10-bit addressing mode. When
Bit 1 of I2CxSCON (ADR10EN bit) is set to 1, then one 10-bit
address is supported in slave mode and is stored in registers
I2CxID0 and I2CxID1. The 10-bit address is derived as follows:
I2CxID0[0] is the read/write bit and is not part of the I
address.
I2CxID0[7:1] = Address Bits[6:0].
I2CxID1[2:0] = Address Bits[9:7].
I2CxID1[7:3] must be set to 11110b.
Master Mode
In master mode, the I2CxADR0 register is programmed with
the I
In 7-bit address mode, I2CxADR0[7:1] are set to the device
address. I2CxADR0[0] is the read/write bit.
In 10-bit address mode, the 10-bit address is created as follows:
I2CxADR0[7:3] must be set to 11110b.
I2CxADR0[2:1] = Address Bits[9:8].
I2CxADR1[7:0] = Address Bits[7:0].
I2CxADR0[0] is the read/write bit.
UCLK
2
C BUS ADDRESSES
2
DIVH = DIVL = 0xCF
DIVH = 0x28, DIVL = 0x3C
is the clock before the clock divider and the clock selected
2
C address of the device.
f
C master in the system generates the serial clock for a
SERIAL
CLOCK
=
2 (
+
DIVH
f
UCLK
)
+
(2
+
DIVL
)
2
C